- Updated GPIO table to match BIOS PV ER3 release.
- Disable SCI for D13 and E00.
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
- Move DEBUG CODE END to later part of the GPIO function in
order to add GPIO prints when required.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixes the KW issue that is reported due to NULL
pointer deference. Moved up the code where CfgData checks for NULL.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixed BDF for UFS device, bus number and function
number are improperly ported and this patch fixed the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the hang seen during a reboot cmd on ADLS DDR4 board.
Setting the DmiMaxLinkSpeed to Auto mode.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
HsPhy feature is only applicable for ADLS and not for others.
Adding a condition to apply only for it.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch added support to get csme boot time performance
data and display it in perf command and also before booting
to linux.
Introduced a board config option BOOT_PERFORMANCE_MASK to control
PcdBootPerformanceMask, BIT 2 now enables printing CSME boot
performance data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Sync from EHL BIOS.
Error: ACPI BIOS Error (bug): AE_AML_BUFFER_LIMIT, Field [IOF2] at
bit offset/length 712/16 exceeds size of target Buffer (664 bits)
Signed-off-by: Randy Lin <randy.lin@intel.com>
Update FSP UPDs and VBT changes as part of the ADLP MR release.
TEST=Tested to boot to OS.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
*Adds code to support the updating
of ACM FW via capsule
*Adds code that disallows for the
roll back of ACM FW
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This patch can reduce the chance of setting SBL_SOURCE when the
SBL root directory is not named as "SblOpen" or when the scripts
are run from the path other than the SBL root directory. Also note
that os.path.abspath() returns the absolute path relative to the
current working directory instead of the real path of __file__.
So in StitchIfwi.py, sblopen_dir was incorrect since the working
directory had been changed before calling stitch().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
FSPT doesn't allow to enable full flash code cache.
Bootloader configures MTRR in non BTG cases to avoid
performance penalty.
This fixes the ADL boot from BP1 partition.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
PSE is enabled by default.
During SBL building, it will check the existance of PSE FW binary.
If it is missing in binaries folder, the PSEF won't be appended in
container list and casue StitchIFWI script fail if it try to update.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Also set the CpuTempSensorReadEnable = 1
It was renamed from PchCpuTempSensorEnable
and removed in commit 44faa431c9
Signed-off-by: Randy Lin <randy.lin@intel.com>
The default FSP UPD value for Lp5BankMode doesn't work
for all the platforms. It would help override it using
SBL configuration data if it is exposed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added changes required for ADLN FSP Sync and
also did the following
1) Added SA config for DDR5 CRB
2) Initialized VBT to enable 2 HDMI and a DP port
3) Moved FSPM config to delta file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This reverts commit 1caacefeb5.
The USB port that does not respond to USB bus enumeration is port 8 on
the newer UPX board. The old UPX board might have different behavior.
The original commit was valid on old UPX board only, and this patch
reverted it. Confirmed the USB error message disappeared on the new
UPX board after the reverting.
Signed-off-by: Maurice Ma <mauricemx.ma@gmail.com>
Only enabled IehMode when IBECC error injection is disabled
Iehmode will cause failure in IBECC error injection test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Match the FSP include path from Board Config to that of
FspBin inf file so it fixes the build issue.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
By default OsLoader payload shell is only available in debug build.
In some case customer also wants to have shell in release build.
So add a BootToShell configuration item to enable shell in release build.
By default BootToShell is set to 0. When it is set to 1 the shell behavior
would be same in release and debug build.
NOTE: user could add this line in platform dlt file to set BootToShell.
GEN_CFG_DATA.BootToShell |1
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch assigns Timed GPIO Cfg Data to the NVS variables
in order for the OS to load this driver.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
* Generate platform build name definition
Same code could be shared by different platforms. At same time,
some platform might need do minor change to the shared code.
In order to support this case, this patch updated the build tool
to generate a macro definition for current build platform name
in a header file. so the shared code could have platform specific
code change with this macro definition.
e.g. add "#define #define PLATFORM_ADLS 1" for ADLS.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [ADLS] update
FspsUpdUpdateLib could be shared by different platform,
use ADLS macro definition instead of PcdAdlLpSupport for
ADLS specific change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
SBL uses PcdMemoryMapEntryNumber to control the max entry
number of memory map info HOB. In some platforms, CML
encountered "Memory map failure" due to the actual entry
number exceeding it. So increase the max to accommodate
the case.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch fixed build issues caused by adding L2QosEnumerationEn UPD
which is not present on other ADL platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The default big core number was set to 8, it has to be overridden if
the CPU number is not 8. Had better set to 0xFF to all active big cores.
Also it mentioned the default value is 0xFF in the help message.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Unlike ADLS, TSN link speed will be coming from the Cfg data.
New TSN GPIO table needed for ADLN board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous commit fe6cf3272 unexpectedly changed the AUTO payload-switching
behavior. This patch restores the behavior to the original design.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Add PchPseAicEnabled and PchUnlockGpioPads in
CfgData_Silicon.yaml file to allow modification
using Config Editor tool.
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Some of the RTCT table entries werent populated due to this
missing UPD setting. Hence, assigning it to the correct value.
TEST= Verified the fix on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch adds control option for TCO timer.
Use case: the control option shall be enabled when Linux hw watchdog
driver (iTCO) is enabled.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds "fs load" command to SBL shell so that it can be
used to load a file from boot media into memory. It also supports
loading file at specified memory address.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Graphics driver in FSP Silicon init is expecting
board related changes for VBT, so moved UpdateVbt
function call before Silicon Init.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Removed RTC logic, it is problematic and should not be used,
all other platforms are not using this logic and
we should remove this from the code
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch added support for ADLN platform.
EC related ACPI changes need to be reinvestigated
as disabling ECAvailable NVS change might be
sufficient to disable EC support in ACPI.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch enables graphics console when entering FWU payload.
FWU progress will show on both graphics console and serial port.
Signed-off-by: kokweich <kok.wei.chan@intel.com>
This patch fixes the test case where when a bad dso is
provided, it will revert back to the default dso settings.
TEST= Ran the test case successfully on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
On TGL, Linux reported ACPI errors on missing PRES method for SATA
port 0. This patch added the missing PRES implementation for all
SATA ports.
This fixed#1497.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL ACPI table does not define any I2C pad or panel. And
it will cause ACPI error for Linux. This patch added conditional
scope for I2C pad and panel reference so that if pad type or panel
type is not defined, these scope will not be used by ACPI.
This fixed#1496.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Fix two errors:
ACPI Error: Aborting method \_SB.PR00.GCAP due to previous error
(AE_INVALID_TABLE_LENGTH)
ACPI Error: Aborting method \_SB.PR00._PDC due to previous error
(AE_INVALID_TABLE_LENGTH)
UEFI BIOS always does dynamic loading, but SBL does static loading
instead.
Signed-off-by: Randy Lin <randy.lin@intel.com>
As part of FSP updates for ADLPtest board, update
Silicon UPD settings.
TEST=Validated boot on the RVP board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
With latest changes for S0ix, PciePm is expecting GetCpuSku and
GetCpuSkuInfo function declaration in header files. Added these
declarations in CpuPcieHsPhyInitLib header file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-S.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for ADL.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
This patch enable S0ix feature in ADLP
1. Ported correct NVS value for ADLP.
2. Ported ACPI value refer to BIOS.
3. Implemented workaround for RP08.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Current TGL platform set 0 as the PCI end bus number in ACPI
MCFG table. And it caused incorrect MMCONFIG range calculation in
Linux. This patch updated the template to use 0xFF as the PCI
end bus number.
It should fix#1481, to be confirmed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-s.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for TGL.
Verified: TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch adds Platform and Silicon support for Alderlake
project. Currently, FSP and microcode are not publicly
available. So build will fail with errors. We will update
the project whenever they are available.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
s0ix feature enabling flag also turn off some FSP configs
so that default SBL image can't detect the onboard Lan
and type c devices.
Signed-off-by: Randy Lin <randy.lin@intel.com>
This patch enhanced GPIO convert tool so that it can handle the
new GPIO template format.
EX:
To convert GPIO from YAML format to CSV format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
Platform\ElkhartlakeBoardPkg\CfgData\CfgData_Gpio.yaml
-of csv -o gpio.csv
To convert GPIO from CSV to YAML format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
gpio.csv -of yaml -o gpio.yaml -t new
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes no activity on UART0 pins when enabling it for serial
communication.
In TGL, there are two UART0 instances (GPP_C8~C11 and GPP_F0~F4) while
one (GPP_F0~F4) is shared with CNVI. This patch enables GPP_C8~C11 as
the UART0 instance to reduce the conflict with CNVI.
This patch also fixes the GPIO pins definition for TGL-H and moves
serial io initialization code to SerialIo.c to simplfy Stage2BoardInitLib.c.
Test: TGL-UP3 RVP and TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
1. Update VERINFO_PROJ_MINOR_VER to 3 for MR3
2. Update PSE SIZE to 0x00030000
3. Removal of PchCpuTempSensorEnable FSP UPD due
FSP update
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Increase CFG_DATABASE_SIZE due to the addition
of up6000 dlt file in SBL EHL cfgdata.
The AddConfigData funciton will return EFI_OUT_OF_RESOURCES
due to insufficient cfgdata size when TCC is enabled.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
IsMarkedBadDso and InvalidateBadDso would be required for all
the platforms that support TCC. And the implementation is also
common, so just move them to common TccLib.
Also updated the implementation to remove SPI flash erase for
InvalidateBadDso().
Signed-off-by: Guo Dong <guo.dong@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch invalidates the DSO region with a marker after
a DSO hang (caused by corrupted DSO) is detected (by WDT timeout).
With the marker, stage1b can know the DSO tuning should be skipped.
The bad DSO mark is defined as both Signature and Size in the
TCCT component header are zero.
With this patch, the previous defined WDT scratchpad bit,
WDT_FLAG_TCC_BAD_DSO, is removed.
TEST=Verified on TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Currently StitchLoader.py is under platform package, and
the common tool BtgSign.py should not depend on that tool.
And BtgSign.py indeed doesn't depend on it, so just update
it to make it could work without StitchLoader.py.
Signed-off-by: Guo Dong <guo.dong@intel.com>
On CFL and CML, the board hook PostMemoryInit was called before
FspMemoryInit API. This should be called afterwards instead.
This patch fixed this issue. It is because of missing "break"
statement. It fixed#1435.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch solves an infinite reset loop issue caused
by bad DSO with the scenario:
After platform reset (due to WDT timeout), FSPm asks
for another reset, but before that, WDT_FLAG_TCC_DSO_IN_PROGRESS
is already cleaned. As a result, in the thrid reset, stage1B
will have no idea about the DSO is corrupted and it
continues boot with Tcc Tuning flow, which causes WDT
timeout reset again.
This patch introduces a WDT_FLAG_TCC_BAD_DSO flag in WDT
scrachpad (bit 18). The flag is a marker that is set when
a bad DSO is detected. The new booting flow for "bad DSO" case
if Tcc_Tuning enabled will be:
1st boot: (after fwupdate)
- TCC_DSO and WDT set by stage1b and stage2
- FSP hangs and trigger WDT reset
2nd boot:
- Stage1b detects "bad DSO" because of WDT and
TCC_DSO_IN_PROGRESS. For this case:
Clear TCC_DSO_IN_PROGRESS and WDT.
Set TCC_BAD_DSO.
Then it continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
- FSPm asks for a reset
3rd boot:
- Stage1b detects "bad DSO" because of TCC_BAD_DSO
It continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
The patch does not remove the 200-sec abnormal boot-up symptom
because the symptom is noticeable to user. So user can be aware
of something wrong (bad DSO).
The "bad DSO" flag will be clear before fwupdate, so a fwupdate
with a correct DSO can solve the 200 sec abnormal boot up time.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Config 1/3 RVP boards can't share same IFWI image
and it is required to adjust the FIT parameters.
Add -o cfg3 to support this.
Signed-off-by: Randy Lin <randy.lin@intel.com>
GPIO payload selection settings can be made
into a platform optional common config. This
will ensure that the options display the same
across all platforms which add support for
the GPIO payload selection feature. Each
platform will need to include the
CfgData_PayloadSelection.yaml and needs to
create their own CfgData_GpioPadGroups.yaml
to provide the list of GPIO pad groups to
select from.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch does the following updates to SmBiosInitLib:
1. Provide AddSmbiosType() to add a SmBios Type header.
2. Provide AddSmbiosString() to append strings to Type header.
3. Move Finalize() to after 'PrePayloadLoading' board init phase.
All Smbios related calls need to be done before this.
4. Modified TGL project to adjust to these changes.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Increase epayload size to 0x00162000 for compilation
error with latest debug version of uefi-payload
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
When multiple USB devices are attached, current SBL will try to
boot the device with index specified by HwPart in the boot option.
However, it is hard to determine the USB device index order since
it depends on which port the device is connected to. Instead, for
USB devices, SBL can try to boot from each of them until the boot
image is loaded successfully or all USB devices have been tried out.
This patch added this support.
To enable this feature, it is required to set the USB boot option
HwPart to 0xFF.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PatchChecker.py still complains lots of files with
trailing whitespace and tabs. This patch addressed these
error reporting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
In order to improve the UEFI payload display performance, it is
desirable to have the framebuffer as write-combining for cache
attribute. This patch added a common API to enable this and it
enabled the GFX framebuffer cache for QEMU and TGL. Other
platforms still need porting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch moved SBL core private data strctures and definitions
into a private header file so that other packages cannot refer
to the private structures.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The patch updates CfgData yaml to align with FSP:
1. correct value range for SaGv
2. remove unused variables: FreqSaGvLow and FreqSaGvMid
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Current GpioLib uses 2 bits from OtherSettings to
configure RxRaw field in GPIO PAD CFG DWORD 0. But
Gpio config templates are missing the option to configure
this feature. This patch adds the option in template.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Current SBL uses DLT file to override the GPIO group id in the
GPIO CFGDATA table because the group ID used in CFGDATA needs to
match the group ID used by GPIO library. This patch decoupled the
GPIO group id with the GPIO library. Instead, a translation was
added to convert the group ID to the value required by the GPIO
library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In certain condition, it is required to use fixed display mode. This
path added a new API SetVbtFixedMode() in BoardSupportLib to provide
such function. It can be used to request a fixed resolution at runtime
to run an application, such as setup screen.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added more fields in QEMU GPIO so that more CFGDATA
related tests can be done on QEMU platform.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When some settings from DSO caused system hang, the WDT
would cause the system reboot. And in the next boot,
SBL would use the default setting by not apply the DSO
values.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled several config options for TGL x64 build so that
64 bit PCI resource can be allocated properly. As part of it, the
related GFX bar read/write has been extended to handle 64bit address.
This has been tested on UPX i11 board. X64 SBL can boot to Ubuntu
properly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes three S0ix issues:
1. a regression caused by commit 20889 where the
FspsConfig->SerialIoUartMode missed configuring for legacy UART
2. failed s0ix when assigning uart port2 as debug port: root caused
by Maurice. He pointed out that several uart properties should
not be reset
This fixed#1314.
3. conflict with TCC/TSN: In TGL, S0ix should be disabled when either
TCC or TSN is enabled. If s0ix is enabled, the patch checks TCC/TSN
enabling status and forces turning off S0ix if TCC/TSN is enabled.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
By default, the boot option 0 has mender OS boot flag set, and it causes
"root=" to be appended to the Linux boot command line. For Ubuntu OS,
it will cause the wrong root fs parameter and prevent it from booting.
This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PCI MEM64 resource in ACPI table so that OS can
re-allocate 64bit PCI resource if required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are too much ERROR level debug message in GPIO library. Since
ERROR level debug message will be stored in final release binary,
it increases the image size. This patch changed the GPIO DEBUG
level to VERBOSE by default to reduce binary size. When debug is
needed, we can change the debug level in the header file to allow
more detailed info.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Removal of disabling AcSplitLock FSP UPD.
The FSP UPD is commented out due to the Yocto hang
issue previously which no longer occured.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
On TGL warm reset flow, current MRC will always do full MRC training.
It is because of wrong PMC rigster was used in platform code to set
and clear the MRC scratch pad bit.
This fixed#1346.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Ubuntu 20.04.3 can support TGL platform. However, current SBL won't
be able to boot without changes. It is caused by following issues:
- GRUB CFG support is not enabled by default
- Payload heap is too small to load the full INITRD image
- USB boot option is set to boot from partition 1 and EXT2 filesystem.
This patch addressed above issues. It has been tested on UPX i11.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed the USB enumeration long delay issue seen on
UPX i11 board. It disabled the malfunction USB port 8.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On UPX, one USB2 port does not respond properly during PCI enumeration.
It needs to be disabled. The current SBL code disabled the wrong port.
It should be port 10 (USB2 index 9).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In the TGL implementation of UpdateFspConfig() in Stage1BBoardInitLib.c,
there are two missing UPD updates that have been validated for TGLH. This
manifested itself when enabling the TCC feature by setting ENABLE_TCC in
BoardConfig.py by reporting a bad VT-d descriptor and hanging.
This patch incorporates these two UPD settings for the TGLH boards.
Signed-off-by: Jim A. Pelner <jim.pelner@intel.com>
During UP Extreme board enabling, trace hub interface was enabled
to help debug. But it should be disabled by default. This patch
fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On TGL UpdateFspConfig() funciton in Stage2BoardInitLib.c has code
path to return early, it will skip all remaining UPD initialization.
The code should always continue the flow to finish the whole
function. This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
1. HD Audio and TSN share pins. These are mutually exclusive features.
2. RVP board should be reworked to support legacy HD Audio mode.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Seems some recent patches may have added additional
size to OS Loader and now the internal pre-commit build
test in Jenkins is failing due to not enough space
for PAYLOAD. Other platforms are also using 29000h
so might be best to increase the CFL value as well.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Current SBL code uses MSR(0xce) to calculate the CPU TSC frequency.
However, it is not very accurate. A better way is to use CPUID to
calculate the TSC frequency. This patch added new API to get accurate
TSC frequency. It also added APIs to allow conversion between time
and TSC ticks.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL build will show lots of FSP files as untracked files.
This patch re-orgnized the rules for .gitignore file so that it
has better control at different folder level. With these new rules
no untracked files will be shown for the FSP and VBT files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On SBL, it can support boot option selection through QEMU command line
"-boot order" parameter. However, it does not work anymore. It was
because of the MAX_BOOT_OPTION_CFGDATA_ENTRY adjustment in other commit.
This patch decoupled internal boot option index with the CFGDATA boot
option index so that it does not have impacts on each other. With this
change, QEMU boot option can be altered through command line again.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Ong Kok Tong