OrgACRN
/
slimbootloader
mirror of https://github.com/slimbootloader/slimbootloader.git
1
0
Fork 0
Code Issues Releases Wiki Activity

[TGL] Add SOC specific memory info 

This patch updated the memory info for TGL platform using the SOC
specific memory map registers.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Maurice Ma 2021-10-25 17:14:51 -07:00
parent 78cdcd8732
commit 4936832cde
7 changed files with 68 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
BootloaderCorePkg/Include/Library/BootloaderCoreLib.h
View File

@ -494,6 +494,8 @@ GetDmaBufferPtr (
/**
This function retrieves system memory info the given type.
@param[in] MemInfoType Memory info type to retrieve.
@retval Value of the required memory info type.
It returns 0 if the required type is invalid.
@ -507,8 +509,11 @@ GetMemoryInfo (
/**
This function sets system memory info for the given type.
@param[in] MemInfoType Memory info type to retrieve.
@param[in] Value The value to set.
**/
UINT64
VOID
EFIAPI
SetMemoryInfo (
IN MEM_INFO_TYPE MemInfoType,

1
BootloaderCorePkg/Include/Library/SocInitLib.h
View File

@ -64,6 +64,7 @@ UpdateResetReason (
**/
VOID
EFIAPI
UpdateMemoryInfo (
VOID
);

9
BootloaderCorePkg/Library/BootloaderCoreLib/BootloaderCoreLib.c
View File

@ -394,7 +394,9 @@ GetDmaBufferPtr (
}
/**
This function retrieves system memory info for the given type.
This function retrieves system memory info the given type.
@param[in] MemInfoType Memory info type to retrieve.
@retval Value of the required memory info type.
It returns 0 if the required type is invalid.
@ -419,8 +421,11 @@ GetMemoryInfo (
/**
This function sets system memory info for the given type.
@param[in] MemInfoType Memory info type to retrieve.
@param[in] Value The value to set.
**/
UINT64
VOID
EFIAPI
SetMemoryInfo (
IN MEM_INFO_TYPE MemInfoType,

3
Platform/TigerlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -38,6 +38,8 @@
#include <TccConfigSubRegions.h>
#include <Library/ResetSystemLib.h>
#include <Library/WatchDogTimerLib.h>
#include <Library/SocInitLib.h>
CONST PLT_DEVICE mPlatformDevices[]= {
{{0x00001700}, OsBootDeviceSata , 0 },
@ -864,6 +866,7 @@ DEBUG_CODE_END();
// Clear the DISB bit after completing DRAM Initialization Sequence
//
MmioAnd32 (PmcMmioBase + R_PMC_PWRM_GEN_PMCON_A, (UINT32)~B_PCH_PMC_GEN_PMCON_A_DISB);
UpdateMemoryInfo ();
break;
case PreTempRamExit:
break;

1
Silicon/TigerlakePkg/Include/Register/SaRegs.h
View File

@ -70,4 +70,5 @@
/// This register must be 1MB aligned when reclaim is enabled.
///
#define R_SA_MC_CAPID0_A_OFFSET 0xE4
#endif

33
Silicon/TigerlakePkg/Include/Register/SaRegsHostBridge.h
View File

@ -60,21 +60,24 @@
#define B_SA_GGC_GGMS_MASK (0xc0)
#define V_SA_GGC_GGMS_8MB 3
///
/// Description:
/// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
///
#define R_SA_BGSM (0xb4)
// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
#define R_SA_BGSM (0xb4)
// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
#define R_SA_TSEGMB (0xb8)
// This Register contains the size of physical memory.
#define R_SA_TOM (0xa0)
#define B_SA_TOM_MASK (0x7ffff00000ULL)
// This 64 bit register defines the Top of Upper Usable DRAM.
#define R_SA_TOUUD (0xa8)
#define B_SA_TOUUD_MASK (0x7ffff00000ULL)
// This register contains the Top of low memory address.
#define R_SA_TOLUD (0xbc)
#define B_SA_TOLUD_MASK (0xfff00000)
///
/// Description:
/// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
///
#define R_SA_TSEGMB (0xb8)
///
/// Description:
/// This register contains the Top of low memory address.
///
#define R_SA_TOLUD (0xbc)
#endif

32
Silicon/TigerlakePkg/Library/Stage1BSocInitLib/Stage1BSocInitLib.c
View File

@ -13,6 +13,7 @@
#include <Library/DebugLib.h>
#include <Library/BoardInitLib.h>
#include <MemInfoHob.h>
#include <CpuRegsAccess.h>
#define TCO_STS_2ND_TIMEOUT BIT1
@ -132,3 +133,34 @@ UpdateResetReason (
}
SetResetReason (ResetReason);
}
/**
Update memory map related info using SOC registers.
**/
VOID
EFIAPI
UpdateMemoryInfo (
VOID
)
{
UINT32 Tolum;
UINT64 Touum;
UINT64 Tom;
// Update system memory info using SOC specific registers
Tom = PciRead32 (PCI_LIB_ADDRESS(SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_TOM));
Tom += LShiftU64 (PciRead32 (PCI_LIB_ADDRESS(SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_TOM + 4)), 32);
Tom &= B_SA_TOM_MASK;
SetMemoryInfo (EnumMemInfoTom, Tom);
Tolum = PciRead32 (PCI_LIB_ADDRESS(SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_TOLUD));
Tolum &= B_SA_TOLUD_MASK;
SetMemoryInfo (EnumMemInfoTolum, Tolum);
Touum = PciRead32 (PCI_LIB_ADDRESS(SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_TOUUD));
Touum += LShiftU64 (PciRead32 (PCI_LIB_ADDRESS(SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_TOUUD + 4)), 32);
Touum &= B_SA_TOUUD_MASK;
SetMemoryInfo (EnumMemInfoTouum, Touum);
}