1. Update BoardID and PlatformID for CRB board
2. Direct return after read board id from smbus to avoid boardid clashing
3. Added ddi config for CRB board
4. Update FSPM UPD due to common value across all sku
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This change makes sure that, during each recovery,
the FW update status structure is cleared and
repopulated
Without this change, in the event that there is
a full recovery and then an interrupted recovery,
the interrupted recovery is unable to resume
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Clear the RTC EN SCI flag to avoid interrupt storming
that cause system hang when using rtcwake method to perform
powre management test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- FSP version - 0C.00.69.74
- Vbt version - 1077
- Microcode version - m_07_90672_00000023
- Minor version updated to '2' for MR2.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
- Increase PlatformMemorySize to get rid of FSP error caused
during Tcc SRAM init.
- Sort the CPUs in ascending order for Tcc validation purpose.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Use the GPIO table from SBL config data instead of
the one from .h file. the .h file will keep there
a while just for reference.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Use a on board switch (Pin B3) as the GPIO to switch
UEFI payload and OsLoader. So update its setting as
GPIO IN for this purpose.
Signed-off-by: Guo Dong <guo.dong@intel.com>
For PAD name (e.g., GPD12), current GpioDataConvert.py get the
pad number using pad_name[4:6]. It should be changed to pad_name[3:5].
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current PlatformNvs parameters are causing the power management
(S3, S4 and S5) in Windows OS. Removing the Nvs parameters will fixed
the issues.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Restore SMM registers was done in the PostPciEnumeration.
so remove the duplicated code in EndOfStages
and call ClearS3SaveRegion() in normal path to avoid
appending multiple restore records.
Signed-off-by: Guo Dong <guo.dong@intel.com>
FSP-S UPD format for THC port assignment was updated, but PEP logic
was using the old format, and causing the PEP constraint to always be
enabled. This issue didn't seem to be causing a problem, but resulted
in noncompliant low power idle constraints.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This Patch fix the build issues due to the increased payload and image size
in windows and linux environment.
- Fixed PAYLOAD size greater than padding size issue for CML.
- Fixed FWUPDATE size greater than padding size issue for EHL.
- Fixed FV image size issue for CMLV,TGL,EHL and ADLS.
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
This patch will let ADLP project to build and stitch images from
open source.
TEST = Smoke-test to boot to Windows/Yocto
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous setting of SW-first CM mode was causing a hang during S3/S4 entry. Likely this setting requires additional ACPI/driver support which is missing.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Remove OS version check in PEPD _STA method. This is a change to the intelpep.sys ASL device (PEPD) for low power idle support. Previously, _STA would always return present/enabled for Win10 even if S0ix config flag was disabled. Changed version always returns status based on S0ix flag. Without this workaround, S4 resume was failing on ADL-N/P/PS.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Use the GPIO table for the test boards.
This change would help fix PCIe device detection from PCIe slot.
Late would change post memory gpio table to SBL cfg data.
Signed-off-by: Guo Dong <guo.dong@intel.com>
- skip the component replacemnt if the component is not located in SBL image
- print the skipped replacement components
- indicate failure through exit status for easily diagnosing problems
when checking stitch config parameters
- add required flash image region 5=EC for new FIT (15.40.26.2632)
- remove 'sata' stitch option since it is no function
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Process Gpio Cfg data from the dlt file instead of the hard-coded
GPIO table.
- The table in the PostMem hdr file is only for reference.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
The patch adds support of "GPD" group when parsing a .h header file.
It also
- adds supports for Pch-N,
- fixes leading whitespaces in h file.
Test commands:
# h to dlt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if example_adls.h -of dlt -p s \
-o out_adls.dlt
# h to yaml
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if example_adls.h -of yaml -p s \
-o out_adls.yaml
# yaml to h
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of h -p s \
-o out_h_from_yaml.h
# dlt to h
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of h -p s \
-o out_h_from_dlt.h
# check: compare example_adls.h and out_h_from_dlt.h
# yaml to txt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of txt -p s \
-o out_txt_from_yaml.txt
# dlt to txt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.dlt -of txt -p s \
-o out_txt_from_dlt.txt
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
The steps of OEM key revocation are:
1. Replace OEM KM (signed with key2) by updating CSME
2. Replace BIOS region (signed with key2)
3. Reboot with new BIOS region (to make key1 inactive)
4. Revoke key1
Before this patch, it requires 2 firmware updates and 2 capsules for
step 1~2 and step 4 respectively. The patch combines them into a single
update/capsule.
To implement the feature, the patch:
1. Double max # of payloads to allow CSME/CSMD/BIOS/CMDI update
in one capsule image.
2. Prevent from failing update of a critical component.
e.g., if step 1(CSME) fails, step 2(BIOS) should be skipped
Verified cases:
Case 1: Capsule having CSMD/CSMD/BIOS/CMDI.
Expectation: successful
$ python BootloaderCorePkg/Tools/GenCapsuleFirmware.py \
-p CSME FWUpdate.bin \
-p CSMD CsmeUpdateDriver.efi \
-p BIOS new_BiosRegion.bin \
-p CMDI cmdi.txt \
...(skip)
Case 2: Capsule having CSME/BIOS/CMDI but no CSMD.
Expectation: no update
Case 3: Inject fault flow (no partition switch after first flash),
Capsule having CSME/CSMD/BIOS/CMDI.
Expectation: no CMDI update
Verification: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- update FSP version to MR4 FSP (09.04.25.11)
- update VBT version to MR4 FSP (244)
- update microcode version to 16
- update EHL platform version to 1.4
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
EHL DMA controllers are hidden at PSF level in reference code,
DMA controllers are reported as ACPI devices if ownership is Host.
So should not check DMA PCI header for DSDT table patching.
Update the change follow EHL reference code.
Signed-off-by: Gavin Xue <gavin.xue@intel.com>
When some settings from DSO caused system hang,
the WDT would cause the system reboot.
And in the next boot, SBL would use the default
setting by not apply the DSO values.
Verify on EHL CRB.
Signed-off-by: Aiman Rosli <muhammad.aiman.rosli@intel.com>
1. Ported IT8659 Sio (Super IO) and DTT (Dynamic Tuning Technology)
for ADL platform
2. Added CfgData to disable or enable the SIO feature
3. Fixed warning for Linux gcc bug -Wmissing-braces in SioChip.c
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- update FSP version to IoT FSP 5143_01_MR6 (0A.00.7B.31)
- update VBT version to IoT FSP 5143_01_MR6 (250)
- update TGLU microcode version to A4
- update TGL platform version to 1.6
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Enable Tcc code path for N series.
- Disable WDT lock UPD since its causing the WDT to expire
even when valid DSO is provided.
- Code clean-up.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
When S0ix feature is enabled, some controllers are disabled
and ethernet/lan is one of them. Hence, disable by default so
that other controllers can be enabled by default.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Found PSDS ACPI table reporting incorrect value
and fixing by referring the BIOS method to retrieve
right value. Also Enable Platform Security Discovery.
Verify on CRB platform.
Signed-off-by: Randy Lin <randy.lin@intel.com>
The patch fixes GPIO group pin to pad issue, caused by GPPC_A0
starts from the bit offset 8 instead of 0 in all registers of
mPchHGpioGroupInfo[0].
The patch also updates the GPIO settings of GPP-A group for TGL-H RVP.
Verified: TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- Updated GPIO table to match BIOS PV ER3 release.
- Disable SCI for D13 and E00.
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
- Move DEBUG CODE END to later part of the GPIO function in
order to add GPIO prints when required.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixes the KW issue that is reported due to NULL
pointer deference. Moved up the code where CfgData checks for NULL.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixed BDF for UFS device, bus number and function
number are improperly ported and this patch fixed the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the hang seen during a reboot cmd on ADLS DDR4 board.
Setting the DmiMaxLinkSpeed to Auto mode.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
HsPhy feature is only applicable for ADLS and not for others.
Adding a condition to apply only for it.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch added support to get csme boot time performance
data and display it in perf command and also before booting
to linux.
Introduced a board config option BOOT_PERFORMANCE_MASK to control
PcdBootPerformanceMask, BIT 2 now enables printing CSME boot
performance data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Sync from EHL BIOS.
Error: ACPI BIOS Error (bug): AE_AML_BUFFER_LIMIT, Field [IOF2] at
bit offset/length 712/16 exceeds size of target Buffer (664 bits)
Signed-off-by: Randy Lin <randy.lin@intel.com>
Update FSP UPDs and VBT changes as part of the ADLP MR release.
TEST=Tested to boot to OS.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
*Adds code to support the updating
of ACM FW via capsule
*Adds code that disallows for the
roll back of ACM FW
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This patch can reduce the chance of setting SBL_SOURCE when the
SBL root directory is not named as "SblOpen" or when the scripts
are run from the path other than the SBL root directory. Also note
that os.path.abspath() returns the absolute path relative to the
current working directory instead of the real path of __file__.
So in StitchIfwi.py, sblopen_dir was incorrect since the working
directory had been changed before calling stitch().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
FSPT doesn't allow to enable full flash code cache.
Bootloader configures MTRR in non BTG cases to avoid
performance penalty.
This fixes the ADL boot from BP1 partition.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
PSE is enabled by default.
During SBL building, it will check the existance of PSE FW binary.
If it is missing in binaries folder, the PSEF won't be appended in
container list and casue StitchIFWI script fail if it try to update.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Also set the CpuTempSensorReadEnable = 1
It was renamed from PchCpuTempSensorEnable
and removed in commit 44faa431c9
Signed-off-by: Randy Lin <randy.lin@intel.com>
The default FSP UPD value for Lp5BankMode doesn't work
for all the platforms. It would help override it using
SBL configuration data if it is exposed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added changes required for ADLN FSP Sync and
also did the following
1) Added SA config for DDR5 CRB
2) Initialized VBT to enable 2 HDMI and a DP port
3) Moved FSPM config to delta file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This reverts commit 1caacefeb5.
The USB port that does not respond to USB bus enumeration is port 8 on
the newer UPX board. The old UPX board might have different behavior.
The original commit was valid on old UPX board only, and this patch
reverted it. Confirmed the USB error message disappeared on the new
UPX board after the reverting.
Signed-off-by: Maurice Ma <mauricemx.ma@gmail.com>
Only enabled IehMode when IBECC error injection is disabled
Iehmode will cause failure in IBECC error injection test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Match the FSP include path from Board Config to that of
FspBin inf file so it fixes the build issue.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
By default OsLoader payload shell is only available in debug build.
In some case customer also wants to have shell in release build.
So add a BootToShell configuration item to enable shell in release build.
By default BootToShell is set to 0. When it is set to 1 the shell behavior
would be same in release and debug build.
NOTE: user could add this line in platform dlt file to set BootToShell.
GEN_CFG_DATA.BootToShell |1
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch assigns Timed GPIO Cfg Data to the NVS variables
in order for the OS to load this driver.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
* Generate platform build name definition
Same code could be shared by different platforms. At same time,
some platform might need do minor change to the shared code.
In order to support this case, this patch updated the build tool
to generate a macro definition for current build platform name
in a header file. so the shared code could have platform specific
code change with this macro definition.
e.g. add "#define #define PLATFORM_ADLS 1" for ADLS.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [ADLS] update
FspsUpdUpdateLib could be shared by different platform,
use ADLS macro definition instead of PcdAdlLpSupport for
ADLS specific change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
SBL uses PcdMemoryMapEntryNumber to control the max entry
number of memory map info HOB. In some platforms, CML
encountered "Memory map failure" due to the actual entry
number exceeding it. So increase the max to accommodate
the case.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch fixed build issues caused by adding L2QosEnumerationEn UPD
which is not present on other ADL platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The default big core number was set to 8, it has to be overridden if
the CPU number is not 8. Had better set to 0xFF to all active big cores.
Also it mentioned the default value is 0xFF in the help message.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Unlike ADLS, TSN link speed will be coming from the Cfg data.
New TSN GPIO table needed for ADLN board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous commit fe6cf3272 unexpectedly changed the AUTO payload-switching
behavior. This patch restores the behavior to the original design.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Sean McGinn