[ADLP] Enable UFS configuration (#1580)
This patch enabled UFS configuration on ADLP platform Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
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@ -352,6 +352,13 @@
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Describe the specific over current pin number of USBC Port N.
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length : 0x0008
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value : {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
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- PchUfsEnable :
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name : Enable PCH UFS
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type : EditNum, HEX, (0x0, 0x1)
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help : >
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Enable/Disable UFS controllers 1 and 2. 0- Disable; 1- Enable.
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length : 0x02
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value : {0x00, 0x00}
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- PchIshI2cEnable :
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condition : $(COND_S0IX_DIS)
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name : Enable PCH ISH I2C pins assigned
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@ -453,5 +460,5 @@
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length : 0x01
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value : 0x1
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- SiliconRsvd :
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length : 0x00
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length : 0x02
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value : 0x00
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@ -652,5 +652,19 @@ UpdateFspConfig (
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DEBUG ((DEBUG_INFO, "Stage 1B S0ix config applied.\n"));
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}
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}
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//
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// Enable ISH incase if UFS is enabled.
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//
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if ((SiCfgData != NULL) && ((SiCfgData->PchUfsEnable[0] == 1) || (SiCfgData->PchUfsEnable[1] == 1))) {
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if (IsPchLp ()) {
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switch (GetPlatformId ()) {
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case PLATFORM_ID_ADL_P_LP4_RVP:
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case PLATFORM_ID_ADL_P_LP5_RVP:
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case PLATFORM_ID_ADL_P_DDR5_RVP:
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Fspmcfg->PchIshEnable = 1;
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}
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}
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}
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}
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@ -1002,8 +1002,8 @@ UpdateFspConfig (
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FspsConfig->TdcTimeWindow[0] = 0x3e8;
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FspsConfig->TdcTimeWindow[1] = 0x3e8;
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FspsConfig->PchLockDownBiosLock = 0x1;
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FspsConfig->UfsEnable[0] = 0x0;
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FspsConfig->UfsEnable[1] = 0x0;
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FspsConfig->UfsEnable[0] = SiCfgData->PchUfsEnable[0];
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FspsConfig->UfsEnable[1] = SiCfgData->PchUfsEnable[1];
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FspsConfig->IehMode = 0x0;
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FspsConfig->PortResetMessageEnable[0] = 0x1;
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FspsConfig->PortResetMessageEnable[1] = 0x1;
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@ -68,6 +68,30 @@ CONST PLT_DEVICE mPlatformDevices[] = {
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.Type = OsBootDeviceNvme,
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.Instance = 1
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},
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{
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.Dev = {
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.PciDev = {
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.PciFunctionNumber = 0,
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.PciDeviceNumber = 18,
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.PciBusNumber = 5,
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.IsMmioDevice = 0
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}
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},
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.Type = OsBootDeviceUfs,
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.Instance = 0
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},
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{
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.Dev = {
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.PciDev = {
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.PciFunctionNumber = 0,
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.PciDeviceNumber = 18,
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.PciBusNumber = 7,
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.IsMmioDevice = 0
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}
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},
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.Type = OsBootDeviceUfs,
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.Instance = 1
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},
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{
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.Dev = {
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.PciDev = {
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