[ADL] Configure MTRR to enable full flash region cache (#1565)
FSPT doesn't allow to enable full flash code cache. Bootloader configures MTRR in non BTG cases to avoid performance penalty. This fixes the ADL boot from BP1 partition. Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
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@ -13,6 +13,7 @@
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#include <Library/PlatformHookLib.h>
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#include <Library/BootloaderCoreLib.h>
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#include <PchAccess.h>
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#include <CpuRegs.h>
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#include <FsptUpd.h>
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#include <PlatformData.h>
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#include <Library/GpioLib.h>
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@ -132,8 +133,12 @@ BoardInit (
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IN BOARD_INIT_PHASE InitPhase
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)
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{
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UINT8 DebugPort;
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GPIO_INIT_CONFIG *UartGpioTable;
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UINT8 DebugPort;
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GPIO_INIT_CONFIG *UartGpioTable;
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UINT32 MsrIdx;
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UINT32 ImgLen;
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UINT32 AdjLen;
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UINT64 MskLen;
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switch (InitPhase) {
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case PostTempRamInit:
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@ -152,12 +157,31 @@ BoardInit (
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PlatformHookSerialPortInitialize ();
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SerialPortInitialize ();
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// Enlarge the code cache region to cover full flash for non-BootGuard case only
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if ((AsmReadMsr64(MSR_BOOT_GUARD_SACM_INFO) & B_BOOT_GUARD_SACM_INFO_NEM_ENABLED) == 0) {
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// FSP-T does not allow to enable full flash code cache due to cache size restriction.
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// Here, MTRR is patched to enable full flash region cache to avoid performance penalty.
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// However, the SBL code flow should ensure only limited flash regions will be accessed
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// before FSP TempRamExit() is called. The combined DATA and CODE cache size should satisfy
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// the BWG requirement.
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MskLen = (AsmReadMsr64(MSR_CACHE_VARIABLE_MTRR_BASE + 1) | (SIZE_4GB - 1)) + 1;
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MsrIdx = MSR_CACHE_VARIABLE_MTRR_BASE + 1 * 2;
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ImgLen = PcdGet32(PcdFlashSize);
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AdjLen = GetPowerOfTwo32(ImgLen);
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if (ImgLen > AdjLen) {
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AdjLen <<= 1;
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}
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AsmWriteMsr64(MsrIdx, (SIZE_4GB - AdjLen) | CACHE_WRITEPROTECTED);
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AsmWriteMsr64(MsrIdx + 1, (MskLen - AdjLen) | B_CACHE_MTRR_VALID);
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}
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break;
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default:
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break;
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}
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}
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/**
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Get size of Platform Specific Data
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@ -26,6 +26,9 @@
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#define MSR_PACKAGE_POWER_SKU 0x614
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#define MSR_BOOT_GUARD_SACM_INFO 0x0000013A
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#define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED BIT0
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///
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/// Local APIC definitions
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///
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@ -37,6 +40,11 @@
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#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_DT_HALO 0x00090670
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#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
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#define CACHE_WRITEPROTECTED 5
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#define MSR_CACHE_VARIABLE_MTRR_BASE 0x200
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#define B_CACHE_MTRR_VALID BIT11
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#ifndef SLE_FLAG
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#ifndef STALL_ONE_MICRO_SECOND
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#define STALL_ONE_MICRO_SECOND 1
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