Commit Graph

1364 Commits

Author SHA1 Message Date
Jason Chen CJ 0cf5142895 remove unused vm_state_info
vm_state_info in struct vm_arch is not used, remove it

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-31 11:27:01 +08:00
huihuang.shi ba1b034e1e fix MISRA-C 243S
Included file not protected with #define, this
feature is required.

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-31 11:26:13 +08:00
Binbin Wu ebea5e5ae4 hv: remove unused API init_cpu
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:55:57 +08:00
Binbin Wu fb1248e5d9 hv: remove cr3 handling from cr_access_vmexit_handler
Guest CR3 read/write operations are not trapped.
Remove CR3 handling in cr_access_vmexit_handler.
Also remove unused API vmx_read_cr3.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:55:57 +08:00
Binbin Wu 2df7b96a23 hv: make control register handling functions to public
Move from vmexit.c to vmx.c
Declare the functions in vmx.h
Rename the functions' name with prefix vmx_.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:55:57 +08:00
Kaige Fu 80a79fed39 HV: Replace printf with pr_acrnlog after logmsg init
There are some massages which is not fatal error but should to print
to serial and sbuf(hvlog) at the same time. pr_fatal is for fatal error
massages and it is not good choice for the situation above.

Introduce a new API pr_acrnlog to deal with the situation. And replace the
following printf with pr_acrnlog for massages should be print to sbuf and
serial. Then developers can get those massages on serial and BTM(Boot Time
Measurement) can use acrnlog to get those massages from sbuf.

BTM refers to Boot Time Measurement which will read acrnlog file to get
timestamps of steps we want.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:49:09 +08:00
Li, Fei1 e0c329e4e9 hv: create vm failed don't panic system
Just return error number to the caller.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:01:56 +08:00
Li, Fei1 6c8fc0a4df hv: remove vm_description_array
When we create an UOS, we didn't indicate the vmid.
Thus we can't get the vm description for the vm
description array.

Instead we use a temporary vm description to save data to
fill the vm structure when crate an UOS. It's uselesss once
UOS has created. So we don't need to maintain vm description
array here for UOS.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:01:56 +08:00
Li, Fei1 3fb7b75eda hv: execute vmxon instruction fail don't panic system
Don't panic system when execute vmxon instruction failed.
And let's follow that only print error info when error return
from library function.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:01:56 +08:00
Li, Fei1 fe4484f5a9 hv: move panic out of hv_main
We cleanup ASSERT. This serial try to only panic when create
SOS failed.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:01:56 +08:00
Junjie Mao 2266e133fb lapic: continuous LVT registers as an array
Pointer arithmetic is currently used to calculate the address of a specific
Local Vector Table (LVT) register (except LVT_CMCI) in lapic, since the
registers are continuously placed with fixed padding in between. However each of
these registers are declared as a single uint32_t in struct lapic, resulting
pointer arithmetic on a non-array pointer which violates MISRA C requirements.

This patch refactors struct lapic by converting the LVT registers fields (again
except LVT_CMCI) to an array named lvt. The LVT indices are reordered to reflect
the order of the LVT registers on hardware, and reused to index this lvt array.

The code before and after the changes is semantically equivalent.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 13:52:11 +08:00
Jason Chen CJ 9a604ed00e correct idt_vectoring_info handling
filter out HW exception and NMI from idt_vectoring_info first:
- queue HW exception through vcpu_queue_exception
- make NMI request through vcpu_make_request
this is a complement patch for previous commit "exception: refine exception
injection path", here take care un-injected vectors for types HW exception &
NMI, the previous commit take care SW exception & external interrupt.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ 7718338008 exception: add vcpu_inject_pf support
add page fault exception injection support

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ 75a03bf0f7 exception: use func vcpu_queue_exception to inject exception
use func vcpu_queue_exception for vcpu_inject_gp and exception_vmexit_handler.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ ebc7ee2e18 exception: refine exception injection path
- inject exception based on exception_info
- inject exception according to priority
- for previous not injected vector - idt_vectoring_info, here only take
  care about types for SW exception & external interrupt, the HW exception
  & NMI will be taken care by vmexit_handler in the following commit "correct
  idt_vectoring_info handling"

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ 277830aba8 exception: add vcpu_queue_exception function
add func vcpu_queue_exception to queue exception based on SDM Vol3 Table 6-5,
which may cause #DF or triple fault

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ 44af2690f6 add triple fault request support
if vcpu meet triple fault, the vcpu should exit.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-30 13:51:49 +08:00
Jason Chen CJ 4607177383 replace pending_intr with pending_req
the pending_intr is not only serving for interrupt but also for different
request including TLB & TMR updating, so change the function & variants
name accordingly.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-30 13:51:49 +08:00
Junjie Mao 16152fad79 HV: debug: stop using ## __VA_ARGS__
It is an extension of GCC CPP to:

* allow omitting a variable macro argument entirely, and
* use ## __VA_ARGS__ to remove the the comma before ## __VA_ARGS__ when
  __VA_ARGS__ is empty.

The only use of ## _VA_ARGS__ is to define the pr_xxx() macros, with the first
argument being the format string and the rest the to-be-formatted arguments. The
format string is explicitly spelled out because another macro pr_fmt() is used
to add to the format string a prefix which is customizable by defining what
pr_fmt() expands to.

For C99 compliance, this patch changes the pr_xxx() macros in the following
pattern.

    - #define pr_fatal(fmt, ...)				\
    -     do_logmsg(LOG_FATAL, pr_fmt(fmt), ## __VA_ARGS__);	\
    + #define pr_fatal(...)					\
    +     do_logmsg(LOG_FATAL, pr_prefix __VA_ARGS__);		\

Reference:

* https://gcc.gnu.org/onlinedocs/gcc/Variadic-Macros.html#Variadic-Macros

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-29 14:13:44 +08:00
Junjie Mao 004d2e2696 HV: treewide: give names to unnamed structs/unions
According to the syntax defined in C99, each struct/union field must have an
identifier. This patch adds names to the previously unnamed fields for C99
compatibility.

Here is a summary of the names (marked with a pair of *stars*) added.

struct trusty_mem:

    union {
        struct {
            struct key_info key_info;
            struct trusty_startup_param startup_param;
        } *data*;
        uint8_t page[CPU_PAGE_SIZE];
    } first_page;

struct ptdev_remapping_info:

    union {
        struct ptdev_msi_info msi;
        struct ptdev_intx_info intx;
    } *ptdev_intr_info*;

union code_segment_descriptor:

    uint64_t value;
    struct {
        union {
            ...
        } low32;
        union {
            ...
        } high32;
    } *fields*;

    similar changes are made to the following structures.
    * union data_segment_descriptor,
    * union system_segment_descriptor,
    * union tss_64_descriptor, and
    * union idt_64_descriptor

struct trace_entry:

    union {
        struct {
            uint32_t a, b, c, d;
        } *fields_32*;
        struct {
            uint8_t a1, a2, a3, a4;
            uint8_t b1, b2, b3, b4;
            uint8_t c1, c2, c3, c4;
            uint8_t d1, d2, d3, d4;
        } *fields_8*;
        struct {
            uint64_t e;
            uint64_t f;
        } *fields_64*;
        char str[16];
    } *payload*;

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-29 14:12:15 +08:00
Junjie Mao ef3cb5ba1c treewide: remove unnecessary unnamed structs/unions
According to the syntax defined in C99, each struct/union field must have an
identifier. This patch removes unnamed struct/union fields that can be easily
expressed in a C99-compatible way.

Here is a summary of structs/unions removed.

struct vhm_request:

    union {
        uint32_t type;                  uint32_t type;
        int32_t reserved0[16];    =>    int32_t reserved0[15];
    };

struct vhm_request_buffer:

    struct vhm_request_buffer {
        union {                         union vhm_request_buffer {
            struct vhm_request ...; =>        struct vhm_request ...;
            int8_t reserved[4096];            int8_t reserved[4096];
        }                               }
    }

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-29 14:12:15 +08:00
huihuang.shi b9660eb9d6 refomatted GET_DATA_SIZE macro
The macro GET_DATA_SIZE's code style is not correct,
it is merged by accident,the Pull Request
<fix "obsolete use of designated initializer without '='">
have two commid id,the second commit changed the ucode.c
by mistake.

Now fixed.
Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-29 14:11:29 +08:00
huihuang.shi 784eb6f189 fix "warning:range expression in switch statements are not standard"
Range expression in switch statement is in gcc extension standard(gcc
manual 6.28),not in c99 standard.
GCC manual 6.28 reference link below:
(https://gcc.gnu.org/onlinedocs/gcc-8.1.0/gcc/Case-Ranges.html#Case-Ranges)

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-25 17:18:34 +08:00
huihuang.shi 2f3953a99a fix "warning:ISO C forbids 'return' with expression,in function returning void"
returning void function must return void.

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-25 15:35:50 +08:00
Zide Chen 8f16faab04 HV: further cleanup of header inclusions
According to the comments in hypervisor:
 " This file includes config header file "bsp_cfg.h" and other
	hypervisor used header files.
	It should be included in all the source files."

this patch includes all common header files in hypervisor.h
then removes other redundant inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Zide Chen d594878e31 HV: cleanup for header inclusions.
used https://gitlab.com/esr/deheader to detect and remove unnecessary
header file inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Jason Chen CJ 1b34870824 guest: quick fix for copy_from/to_vm
h_ptr need update from second page walk

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-25 09:43:08 +08:00
Li, Fei1 34445008c2 hv: add non-lock bitmap operation
Add __bitmap_set/clear,
__bitmap_test_and_set/clear.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-25 09:42:03 +08:00
Li, Fei1 efb60e2726 hv: refine bit scan API
Rename
bsrl to bsr
bsrq to bsr64
bitmap_ffs to fls64
get_first_zero_bit to ffz64

Remove
ffsl

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-25 09:42:03 +08:00
Li, Fei1 57d0bf3b7c hv: refine bitops
Rename bitmap_clr to bitmap_clear
Rename bitmap_isset to bitmap_test
Remove bitmap_setof

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-25 09:42:03 +08:00
huihuang.shi d3ef8ae5cb fix "warning ISO C forbids omitting the middle term of a?:expression"
According to the C99 manual 6.5.15
syntax conditional-expression
  logical-OR-expression
  logical-OR-expression ? expression :conditional-expression

above bnf rules requires expression not be none

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-24 13:43:53 +08:00
huihuang.shi 64d2efcfaf fix "obsolete use of designated initializer without '='"
According in C99 manual 6.7.8,'=' is required.

Signed-off-by: huihuang.shi <huihuang.shi@intel.com>
2018-05-24 13:43:53 +08:00
Jason Chen CJ 67dfec8799 vmexit: refine vmexit loop
- move vmexit handling into vmexit_handler
- add error handling, failure will inject #GP

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-24 13:42:19 +08:00
Jason Chen CJ 2ff7bf826e page walk during copy_from_vm/copy_to_vm
there are data transfer between guest(GPA) & hv(HPA), especially for
hypercall from guest.

guest should make sure these GPAs are address continous, but hv cannot
assure HPAs which mapped to these GPAs are address continous, for example,
after enable hugetlb, a contious GPA range could come from two different
2M pages.

this patch is handling such case by doing gpa page walking during
copy_from_vm & copy_to_vm.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-24 13:42:19 +08:00
Binbin Wu 744e09bc7e hv: define 4 vcpu modes
move enum vm_cpu_mode to guest.h
move enum vm_paging_mode to guest.h
replace REAL_MODE with CPU_MODE_REAL
replace PAGE_PROTECTED_MODE with CPU_MODE_64BIT

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-24 10:16:48 +08:00
Yonghua Huang cb262286c6 HV: add NULL pointer check in 'vm_fixup()' function.
- to clear security warning.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-24 10:16:15 +08:00
Mingqiang Chi 7c9cc6bcd4 hv:Merge dump_interrupt and dump_exception to a commond API
merge these two APIs to 'dump_intr_excp_frame'

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-23 13:38:52 +08:00
Mingqiang Chi 8384ed2564 hv:rename data structure intr_ctx
rename intr_ctx to intr_excp_ctx

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-23 13:38:52 +08:00
Yonghua Huang fbaff2aa35 HV:remove redundant field 'mmio' from 'struct emul_cnx'
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-23 11:43:56 +08:00
Yonghua Huang 03ae242eb7 HV:initialize variables before reference in vmx.c
- to avoid complains from code static scan tool

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-22 17:16:07 +08:00
Mingqiang Chi ccc1c25e88 hv:Use exception vector MACRO instead of hardcode
Now use hardcode when inject GP/NMI to guest,
replace it with MACRO.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-22 16:42:38 +08:00
Yonghua Huang aee1931ee6 HV: refine 'decode_instruction() function
update:
   1. remove 'struct mem_io *'from input arguments
   2. return 'opsize' instead of status.
   3. rename 'vmm_decode_instruction()'

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-22 16:41:19 +08:00
Jason Chen CJ 05f8fd701a hypercall: do not allow hypercall from UOS except trusty
only trusty related hypercall will come from UOS, others should come from VM0

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-22 11:38:04 +08:00
Jason Chen CJ f505f338bd hypercall: only allow hypercall from RING-0
only allow hypercall from RING-0

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-22 11:38:04 +08:00
Jason Chen CJ c09b9aa9c1 exception: only trap #MC
HV only print out message for #MC then inject it back to guest.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-22 11:10:15 +08:00
Binbin Wu d8d6176266 hv: fix general protection injection
Exception type is missing when inject a #GP.
GP should be injected even when guest irq disabled.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2018-05-22 10:39:56 +08:00
Mingqiang Chi 2175bcafa1 hv: replace _EC with _ERROR_CODE in VMCS field
EC is not clear, replace it with ERROR_CODE.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-21 15:11:23 +08:00
Yin Fengwei 6ef48fa30e hv: Add reboot shell command
To trigger warm reboot for debugging.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <Eddie.dong@intel.com>
2018-05-18 16:38:40 +08:00
Yonghua Huang 0e5f7cb91c hv: bugfix - MMIO access size was not properly initialized.
- MMIO access size is not initialized before
  instruction emulation.
- rename 'analyze_instruction()' to 'decode_instruction()'

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-18 16:37:44 +08:00
Li, Fei1 edb26a7e17 hv: refine the left atomic operation
rename atomic_cmpxchg_int to atomic_cmpxchg
replace atomic_cmpset_long with atomic_cmpxchg64
rename atomic_readandclear_long to atomic_readandclear64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 1f3da93e74 hv: refine atomic_load/store_xxx name
rename atomic_load/store_xxx32 to atomic_load/store
rename atomic_load/store_xxx64 to atomic_load64/store64

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 336a8883db hv: remove atomic_add/subtract API
add atomic_inc(64)/dec(64) API.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 fadaf14a94 hv: refine atomic_xadd
1. rename atomic_xadd_int to atomic_xadd, add atomic_xadd64.
2. add atomic_add/sbu64_return, atomic_inc/dec64_return.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-18 10:52:31 +08:00
Li, Fei1 bd3f3b00f7 hv: fix incorrect use of atomic_set_xxx
1. vpic_wire_mode no need to atomically set its value.
2. uart open conut want to atomically set its value not atomically set
its bits.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:52:31 +08:00
Mingqiang Chi b3126bdc11 hv: Check ept rwx misconfigurations
Check ept rwx misconfigurations when config memory attribute,
if misconfig it will assert.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-18 10:51:33 +08:00
Yonghua Huang 25219e29a5 HV: refine EPT violation VM-exit handler
- refine EPT violation vmexit handler
- add check for mmio access that spans devices

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-17 15:35:22 +08:00
Victor Sun a6780652f3 HV: operate schedule lock on correct vcpu
Lock should be on target vcpu in function pause_vcpu(), not current vcpu.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-17 15:34:59 +08:00
Jason Chen CJ 71e1ae17ce hypercall: add set_memmaps hypercall support
Add set_memmaps hypercall to support multi regions memmap.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-17 15:34:18 +08:00
Jason Chen CJ a6ff3a9bdc vm: allocated all pcpus to vm0 at the beginning
allocated all pcpus to vm0 to handle possible AP wakeup flow for all cpus,
as we pass org ACPI table to VM0 - that means VM0 can see all CPUs.

SOS(VM0) start expected CPUs through "maxcpus=" kernel cmdline option.

During first hypercall from SOS, calling vm_fixup to free un-expect-enabled
vcpus from VM0.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-17 10:23:27 +08:00
Jason Chen CJ d2a7a9c91d uefi: remove warkaround for AP wakeup
remove sipi_from_efi_boot_service_exit & efi_deferred_wakeup_pcpu workaround
for uefi boot flow

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-17 10:23:27 +08:00
Jason Chen CJ 953f6b5b1b vlapic: kick AP for INIT-SIPI sequence
wakeup AP need INIT-SIPI-SIPI sequence in old time, now we only need
INIT-SIPI.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-17 10:23:27 +08:00
Edwin Zhai e1bb372763 HV: increase UOS VIOAPIC pin count
To avoid UOS virtual GSI sharing

Signed-off-by: Edwin Zhai <edwin.zhai@intel.com>
2018-05-16 15:09:48 +08:00
Yonghua Huang 69d9918ddc remove potential using default i/o handler
- device driver should register valid i/o handlers
  in any cases, avoid referencing to default handler

- remove i/o handler test code as they shall
  never be NULL.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 18:03:34 +08:00
Yonghua Huang c597a0fc2f I/O VM-exit handler cleanup
- add check for spanning i/o devices access
- remove ASSERT in I/O instr. VM exit handler

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 18:03:33 +08:00
Zhao Yakui 263fafe819 HV: Initialize one variable to fix the compiling warning
If the optimization option is enabled, it is possible that one variable is
not initialized before using in the get_vioapic_info. (In fact the warning is
bogus)
This is only to reduce the compiling warning.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2018-05-15 18:03:33 +08:00
Zhao Yakui 698b53adc4 HV: Add one correct Descriptor_table struct to configure VMCS
Now one uint64_t type is used to obtain the corresponding descriptor_table
for GDT/IDT. This will cause the stack protect corruption under -O2.
So the descriptor_table struct is added to configure the GDT/IDT of VMCS.

V1->V2: Move the descriptor_table into vmx.h header file
And its type is renamed from dt_addr_t to descriptor_table.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Zhao Yakui b2cadfecdf HV: Fix the incorrect operand-constraints for inline assembly
The RFLAGS will be touched in some inline assembly.(exec_vmxon/
RFLAGS_RESTORE). The "cc" constraint should be added. Otherwise
it won't be handled under -O2 option.
And "%%XXX" register should also be added into constraints.
Otherwise it will be optimized incorrectly.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Li, Fei1 9dd7d27737 hv: vlapic_timer: refine vlapic tscdeadline timer
Add vlapic_create_timer/vlapic_reset_timer to setup/reset a timer.
Add vlapic_update_lvtt to disarm timer when mode changes.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Li, Fei1 ea54216116 hv: vlapic_timer: add vlapic timer mode API
Add vlapic_lvtt_oneshot, vlapic_lvtt_masked
rename vlapic_periodic_timer to vlapic_lvtt_period
rename VLAPIC_TSCDEADLINE to vlapic_lvtt_tsc_deadline

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Li, Fei1 8ec78f8efc hv: vlapic: coding refine
Using __func__ instead of function string name.
Using tab instead of more whitespace.
Using macro instead of numeric constants.
Remove unnecessary function declaration.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Li, Fei1 b9971c206f hv: vlapic_timer: remove vlapic one-shot/periodic timer implement
These code is useless since it just pseudocode. Current it doesn't
support vlapic one-shot/periodic timer.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Li, Fei1 5df2efad4a hv: timer: make the timer list be ordered
make the timer list be ordered to speed up expried timer
process and next timer event finding.

Add timer would not schedule timer unless it's the next
timer event.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 18:03:33 +08:00
Zide Chen 6f97a14398 HV: Enable CR0.WP
Page fault could be raised if writing to read-only pages. This is
useful for debugging.

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-15 17:25:59 +08:00
lijinxia 3b6fe5782d Revert "HV: Prepare cpu_secondary.S for AP trampoline code relocation"
This reverts commit bfa67fa6a0.
2018-05-15 17:25:59 +08:00
lijinxia b3dd135ed3 Revert "HV: added memory allocation functions for AP trampoline code relocation"
This reverts commit 41b83bb20b.
2018-05-15 17:25:58 +08:00
lijinxia f8fbdbe7ec Revert "HV: Make AP trampoline code relocatable"
This reverts commit 31bf2befbf.
2018-05-15 17:25:58 +08:00
lijinxia 0c5956beb1 Revert "HV: adjust the base address of guest initial page tables"
This reverts commit 4aab1ea80d.
2018-05-15 17:25:58 +08:00
Zide Chen 6de5b0478c HV: adjust the base address of guest initial page tables
V2->V3: Updated variable name: trampoline_code_paddr
V1->V2: changed variable name: init_ap_code_addr

These page tablea are sitting right after the trampoline code, so adjust it according to
the actual loaded address for trampoline code

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Zide Chen fe6397d9d8 HV: Make AP trampoline code relocatable
V3->V4: Updated function/variable names for accurancy
V2->V3: Changed a few function/variable names to make it less confusing
V1->V2: removed the unneccesary cache flushing

- For UEFI boot, allocate memory for trampoline code in ACRN EFI,
  and pass the pointer to HV through efi_ctx
- For other boot, scan E820 to allocate memory in HV run time
- update_trampoline_code_refs() updates all the references that need the
  absolute PA with the actual load address

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Zide Chen ceb3076b69 HV: added memory allocation functions for AP trampoline code relocation
V2->V3: Fixed the booting issue on MRB board and removed the restriction
        of allocate memory from address 0

1) Fix the booting from MRB issue
-#define    CONFIG_LOW_RAM_SIZE 0x000CF000
+#define    CONFIG_LOW_RAM_SIZE 0x00010000

2) changed e820_alloc_low_memory() to handle corner case of unaligned e820 entries
  and enable it to allocate memory at address 0
+		a length = end > start ? (end - start) : 0;

-       /* We don't want the first page */
-       if ((length == size) && (start == 0))
-           continue;

3) changed emalloc_for_low_mem() to enable to allocate memory at address 0
-       /* We don't want the first page */
-       if (start == 0)
-           start = EFI_PAGE_SIZE;

V1->V2: moved e820_alloc_low_memory() to guest.c and added the logic to
        handle unaligned E820 entries

emalloc_for_low_mem() is used if CONFIG_EFI_STUB is defined.
e820_alloc_low_memory() is used for other cases

In either case, the allocated memory will be marked with E820_TYPE_RESERVED

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Zide Chen 9323f811ea HV: Prepare cpu_secondary.S for AP trampoline code relocation
V1->V2: removed CONFIG_LOW_RAM_START and added ".org 0" to
cpu_secondary.S

The assumption is trampoline code is relocated while HV is not, so:

trampoline code is built at address 0, and CS register is updated
by SIPI to reflect the correct vector

in real mode part, added extra pointers for page tables and long jump buffer
so it's possible for HV code to patch the relocation offset

in long mode part, use absolute addressing when referring HV symbols,
and use relative addressing for symbols within trampoline code

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Zide Chen eebf5fec6f HV: correct the handling of MU_MEM_ATTR_READ MMU flag
Currently config_page_table_attr() treats MMU_MEM_ATTR_READ exactly as
MMU_MEM_ATTR_BIT_READ_WRITE for PTT_HOST, so even when MMU_MEM_ATTR_WRITE
is not used, the R/W bit in PTE is still being set

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-15 17:25:58 +08:00
Yonghua Huang e8d5a497f3 refine external interrupt VM exit handler
- According to Intel SDM 24.9.2,Vol3, should check the
  validity of "VM-exit interruption information" before
  extracting the vector of interrupt.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:58 +08:00
Yonghua Huang 121d14a616 rename 'req_buf' field in 'struct vm_sw_info'
- rename it to 'io_shared_page' to keep consistent
   with ACRN HDL foils.

 - update related code that reference this data structure.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:58 +08:00
Yonghua Huang 85716e8b01 security: fix issues reported by Klocwork
- NULL pointer reference risk
 - buffer overflow risk

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:57 +08:00
Li, Fei1 b61e6af228 hv: cpuid: don't reference the crossed array
We should consider the boundary condition although we didn't
access it.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:57 +08:00
Yan, Like ccc67ceae4 hv: add build type and detail time to version string
- Add "DBG" or "REL" to indicate the DBG build or REL build explicityly;
- Change the build time format to "%F %T".

Example:
HV version 0.1-rc4-2018-04-28 14:20:32-b2d7282-dirty DBG build by like

Change-Id: Ib410064b0a6603e3c90f30dffa722237c07fc069
Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun 55bced400e HV cleanup: assert on vm setup cpu px
Make assert on max px cnt of boot cpu data, since it shouldn't happen if
px data is properly initialized in boot process.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun 765805da21 HV cleanup: move iobitmap ini out of loop
The initial of iobitmap pointer should be moved out of loop since address
is sequentially incremented.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun c2c1932a65 HV Cx: add cx data of bxt j3455 SOC
This is cx data for APL NUC.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun 8b29ce1991 HV Cx: allow guest to access host idle port
with this patch guest could access idle io port and enter idle normally.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun 1c3b7a629a HV Cx: load cx data while create VM
Each VM would have its own Cx data, for now we copy it from boot_cpu_info.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Victor Sun 373a828058 HV Cx: load cx data to boot_cpu_data when boot
The cx data is hardcoded within HV, load it to boot_cpu_data when HV boot.
The patch provide a3960 soc cx data for example.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:57 +08:00
Jason Chen CJ c0d4b90415 ptdev: change remapping entry from virtual to physical based
currently, pass-thru devices are managed by per-vm's remapping entries
which is virtual based:
- MSI entry is identified by virt_bdf+msix_index
- INTx entry is identified by virt_pin+vpin_src
it works but it's not a good design for physical resource management, for
example a physical IOAPIC pin could belong to different vm's INTx entries,
the Device Model then must make sure there is no resource conflict from
application's level.

This patch change the design from virtual to physical based:
- MSI entry is identified by phys_bdf+msix_index
- INTx entry is identified by phys_pin
The physical resource is directly managed in hypervisor, a miss adding
entry will be found by hypervisor and return error message with failure.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:57 +08:00
Zide Chen a39509a8fe HV: fixed the issue of AP initialization code can't be loaded to address high than 64K
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-15 17:25:57 +08:00
Li, Fei1 ac253f8c60 hv: timer: add periodic timer setup support
and add MIN_TIMER_PERIOD_US for limit periodic timer frequency.
Now it's set to 500 us.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 9bfa574a27 hv: timer: restruct add_timer/del_timer API
add initialize_timer to initialize or reset a timer;
add_timer add timer to corresponding physical cpu timer list.
del_timer delete timer from corresponding physical cpu timer list.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 be9f4ee9e6 hv: timer: pass timer callback function parameter by pointer
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 dace32eca1 hv: timer: add calibrate tsc hz by cpuid 0x15
Get tsc hz by cpuid 0x15 if we supported, otherwise
calibrate tsc by pit timer.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 cfc87903b2 hv: cpuid: add cpuid_level
Get maximum input value for basic cpuid information.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 7f4332f539 hv: timer: rename cpu/cpu_id to pcpu_id
timer is physical cpu related.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong>
2018-05-15 17:25:56 +08:00
Li, Fei1 d129659ecd hv: timer: remove statistics for timer
Since there no dump related API.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Yin Fengwei 0287ac4a99 hv: Not to destroy ept of trusty memory if it's not initialized.
If guest reboot is issued before trusty init hypercall is issued,
we shouldn't destroy ept fo trusty memory because the ept is not
created yet.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-05-15 17:25:56 +08:00
Zheng, Gen 1c57adc8b3 hv: bug fix on synchronizing with APs
Using eax will truncate the high 32bit part of 64bit virtual address.
And the type of sync is unsigned long, so using rbx instead of ebx.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2018-05-15 17:25:56 +08:00
Zhao Yakui b37c049ef4 HV: Use mmio_read/write_long for IOAPIC mmio-access
This is to do the clean-up of IOAPIC mmio-access. Use the same API to
access the IOAPIC register. At the same time it also helps to avoid the
optimization in direct access mode.(The volatile is already added in
mmio_read_long/mmio_write_long)

V1->V2: Follow Fengwei's suggestion to use the mmio_read/write_long

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by:  Yin Fengwei <fengwei.yin@intel.com>
2018-05-15 17:25:56 +08:00
Li, Fei1 1b1f723c7b hv: add hardware_detect_support to detect which hardware we support
Now just add some basic feature/capability detect (not all). Vapic
didn't add here for if we must support vapic then the code which
for vapic not supported must remove, like mmio apic r/w.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Victor Sun c3374a519a HV: code cleanup for cpu state
Split pm.c from cpu_state_tbl.c to put guest power management related
functions, keep cpu_state_tbl.c to store host cpu state table and
related functions.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:56 +08:00
Minggui Cao 9dbcf7afaf remove deadcode of timer
the code is used to debug before, not used now.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Minggui Cao 8a8b1a47ba remove timer spinlock
for timer list is operated by per-cpu; and no interrupt
service operates it too. So it's unnecessary for spinlock.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Jason Chen CJ a1c6c24248 vm load: add SOS cmdline option for hugetlb
adding "hugepagesz=1G" and "hugepages=X" into SOS cmdline, for X, current
strategy is making it equal
	e820_mem.total_mem_size -CONFIG_REMAIN_1G_PAGES
if CONFIG_REMAIN_1G_PAGES is not set, it will use 3 by default.

CONFIG_CMA is added to indicate using cma cmdline option for SOS kernel,
by default system will use hugetlb cmdline option if no CONFIG_CMA defined.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:56 +08:00
Jason Chen CJ 71ee5ef6c8 mmu: refine function check_mmu_1gb_support
change its input from map_params to page_table_type, and make it as a
public API.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:56 +08:00
Minggui Cao ac5da17e52 enable rdtscp instruction for guest OS all vCPUs
before just AP can run "rdtscp" intruction, if run it on BSP,
it will cause "illegal instruction"; now align BSP & AP.
also remove duplicated code.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang 3c119e124a check validity of 'VM-exit Int-Info' before extracting vector
1. exception vector and other information
   can be extracted from 'VM-Exit Interrupt-Information'
   field of VMCS only if bit31 (Valid) is set.
   -Intel SDM 24.9.2, Vol3

2.  Rename 'exit-interrupt_info' to 'idt_vectoring_info'
    in 'struct vcpu_arch', which is consistent with
    SDM 24.9.3, Vol3

3. 'IDT-vectoring information' in VMCS is 32bit
    -Intel SDM 24.9.3, Vol3

    Update the type of 'idt_vectoring_info' in
    'struct vcpu_arch'from 'uint32_t' to 'uint64_t'.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen c5f860e1cb MMU: bug fix on operating va <=> pa convertion
Before referencing to physical address of devs such as lapic, ioapic,
vtd, and uart, switch to virtual address.
Use a phisical address of pml4 to write CR3.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen d02f4d4a5f refine: change the address arguments type of mmio access api
Change the address arguments type of mmio access api from uint64_t
to void*.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang 11d0e59b3e revise type of 'exit_reason' and 'inst_len' in vcpu_arch
SDM 24.9.1 Volume3:
 - 'Exit reason' field in VMCS is 32 bits.

 SDM 24.9.4 in Volume3
 - 'VM-exit instruction length' field
   in VMCS is 32 bits.

 This patch is to redefine the data types of above fields
 in 'struct vcpu_arch' and udpate the code using these
 two fields.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:55 +08:00
Li, Fei1 4116ddd2a0 hv: mmu: replace cpu feature/capability detect with cpu_has_cap
Since we get cpu feature/capability in boot_cpu_data at boot initialization,
then there no need to get this feature/capability using cpuid again.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:55 +08:00
Li, Fei1 80d194cfb5 hv: vmx_capability: add cpu_has_vmx_ept/vpid_cap API
Refine and simple vmx_capability API defination.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:55 +08:00
Li, Fei1 d7d2ef8c88 hv: xsave: remove is_xsave_supported
Update X86_FEATURE_OSXSAVE when enabled and replace is_xsave_supported
with cpu_has_cap(X86_FEATURE_OSXSAVE).

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:55 +08:00
Li, Fei1 6560ff367c hv: cpu: add cpu_has_cap() API
Add cpu_has_cap API for cpu feature/capability detect instead of
add get_xxx_cap for each feature/capability detect.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang bb011a4316 rename vmexit handlers
this patch is to align the suffix of the handlers' name.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:55 +08:00
Zheng, Gen 6b1782b360 refine: remove redundant data type definition
remove data defination of mmio_addr_t, vaddr_t, paddr_t,
and ioport_t.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:54 +08:00
Yonghua Huang 9b37e1464c add IO requrest 'req_buf' check before reference
This address maybe invalid if a hostile address was set
in hypercall 'HC_SET_IOREQ_BUFFER'.it should be validated
before using.

Update:
  -- save HVA to guest OS's request buffer in hyperviosr
  -- change type of 'req_buf' from 'uint64_t' to 'void *'
  -- remove HPA to HVA translation code when using this addr.
  -- use error number instead of -1 when return error cases.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:27 +08:00
Fei Jiang 3a3aeac09f VMX: change PAT register default value
This is workaround patch to resolve Disti performance issue.
In kernel 4.14, PAT is skipped to initialize if MTRR is not enabled,
while graphics driver need set WC to GGTT memory to accelerate memcpy,
if PAT is not initialized, default PAT register will treat UC- as
uncacheable, which will impact gfx performance. Change PAT default
register value to treat UC- as WC to workaroud this problem.

Revert me when PAT/MTRR strong correlation is removed in kernel.

Signed-off-by: Fei Jiang <fei.jiang@intel.com>
2018-05-15 17:25:27 +08:00
Zheng, Gen 52c020c6f0 VMX: bug fix on operating vmx
Switch all the referenced virtual address to physical address
include ept mapping, vmcs field, vmxon, vmclear, and vmptrld.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Chen, Jason Cl <jason.cj.chen@intel.com>
Reviewed-by: Yakui, Zhao <yakui.zhao@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:25:27 +08:00
Zheng, Gen 7ed446e63b ptdev: bug fix on operating list
Before using a node of list, initialize it.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Yakui, Zhao <yakui.zhao@intel.com>
Reviewed-by: Chen, Jason Cl <jason.cj.chen@intel.com>
2018-05-15 17:25:27 +08:00
Minggui Cao 72b2cb1fa7 remove deadcode of rdtsc_handler/rdtscp_handler
Guest OS rdtsc/rdtscp doesn't trap into hypervisor, so remove them.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 1e2c201827 vtd: add page allocation check for root_table & context_table
if failed to allocate page structure for root_table or context_table,
ASSERT system and return.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 4ea7588241 vtd: context_table_addr should be hpa
add necessary HPA2HVA/HVA2HPA transition for context_table_addr

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 403076e6b9 vtd: dmar_uint->root_table_addr should be hpa
add necessary HPA2HVA/HVA2HPA transition for root_table_addr

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ ebba622d78 mmu: add mmu invlpg support
when host mmu got updated, it should invalidate TLB & page-struct cache.

currently, there is no mmu update will be done after any AP start, so the
simplest way(to avoid shootdown) is just do invlpg for BSP.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 2d6c75408e mmu: refine the checking of entry present
- change the input param of check_page_table_present from struct map_params
  to page_table_type
- check EPT present bits misconfiguration in check_page_table_present
- change var "table_present" to more suitable name "entry_present"

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 60425f91b4 mmu: add ept execution only capability check
check IA32_VMX_EPT_VPID_CAP MSR to see if ept execution only capability
is supported or not

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ b7d57a946b cpu: change cpu_halt name to cpu_dead
cpu_halt actually mean cpu dead in current code, so change it with
more clear name.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:25:27 +08:00
Jason Chen CJ 96f7ff3be1 cpu: add physical cpu active bitmap support
use pcpu_active_bitmap presents which cpu is active

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:25:26 +08:00
Binbin Wu d0c773f22d vtd: fix memory coherency issue of vtd table
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:26 +08:00
Jason Chen CJ f98a7ca90a vlapic: apicv_get_apic_access_addr should get hpa
APIC-access page which write into VMCS should be hpa

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Jason Chen CJ 241efb2da6 vlapic: apicv_get_apic_page_addr should get hpa
virtual-ACPI page which write into VMCS should be hpa

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Qi Yadong ef0c5ec2e3 hv: cache tsc_offset
Guest write tsc: cache the offset into run_context.tsc_offset;
Guest read tsc : use run_context.tsc_offset to calculate guest_tsc.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Mingqiang Chi 9aa9a77457 mmu:create temporary page tables for guest at run time
Before this patch, guest temporary page tables were generated by hardcode
at compile time, HV will copy this page tables to guest before guest
launch.

This patch creates temporary page tables at runtime for the range of 0~4G,
and create page tables to cover new range(511G~511G+16M) with trusty
requirement.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Qi Yadong 7430074a12 trusty: initialize tsc_offset to zero
Per trusty design, trusty requires a monotonic increasing
secure tick(TSC) at run time. This secure tick will used
to mitigate password/pin force attack, control key expiration,
etc.

Currently, the TSC_OFFSET is enabled. And guest will got
(host_tsc + tsc_offset) when execute rdtsc/rdtscp/rdmsr to
aquire tsc value. The host_tsc is always keeping increasing
during the runtime.

So initialize tsc_offset of trusty to 0 will ensure the
secure tick feature.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ bf36022ce9 ept: change eptp to PA
eptp should be record as PA.

this patch changed nworld_eptp, sworld_eptp and m2p eptp to PA type,
necessary HPA2HVA/HVA2HPA transition is used for them after the change.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ 8682552273 mmu: identify VA and PA in mmu.c
- read/write page table entries should use VA which defined as "void *"
- the address data in page table entries should us PA which defined as
  "uint64_t"

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun 24ea869e25 HV: add px data of bxt j3455 SOC
The cpu model name of "Intel(R) Celeron(R) CPU J3455 @ 1.50GHz" is used for
APL NUC which is in Acrn official suport list.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun 7647517a15 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun 1d0d4d3185 HV: add hypercall interface of get vcpu state data
We can use this interface for VHM to pass per-cpu power state data
to guest per its request.

For now the vcpu power state is per-vm, this could be changed if
per-cpu power state support is required in the future.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun 0e2b9fc7fa HV: setup px info when create vm
The vm px info would be used for guest Pstate control.
Currently it is copied from host boot cpu.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun a28fbd15b5 HV: load cpu px data in boot
The patch takes Intel ATOM A3960 as example that hard code all Px info
which is needed for Px control into Acrn HV and load it in boot process.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun 4cd2717038 HV: add cpu model name
The cpu model name would be used to distinguish which hard coded data
need to be loaded to boot_cpu_data;

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ 878b5a0466 mmu: refine functions for invept
- rename mmu_invept to invept
- panic if HW doesn't support invept

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ a68850e00f mmu: replace ASSERT with panic in fetch_page_table_offset
all callers for fetch_page_table_offset should already make sure
it will not come to an unknown table_leve, so just panic here.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ c2f86f23c3 mmu: refine functions walk_paging_struct & update_page_table_entry
- walk_paging_struct should return sub_table_addr, if something wrong,
  it return NULL
- update_page_table_entry should return adjusted_size, if something wrong
  it return 0

the change is valid under release version, as at that time, ASSERT in
walk_paging_struct is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ bb82504f05 mmu: refine functions get_table_entry & obtain_last_page_table_entry
- remove unused map_params in get_table_entry
- add error return for both, which is valid under release version,
  as at that time, ASSERT in get_table_entry is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ cbcc7c0db3 mmu: refine function break_page_table
function break_page_table should return next_level_page_size, if
something wrong, it return 0.

the change is valid for release version, as at that time ASSERT()
in break_page_table is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ 6454c7be6b mmu: refine function map_mem_region
function map_mem_region should return mapped_size, if something wrong,
it return 0.

the change is valid for release version, as at that time ASSERT()
in map_mem_region is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ fa3e424fcf mmu: refine functions modify_paging & map/unmap/modify mem
add error return for all, which is valid under release version,
as at that time, ASSERT in modify_paging is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
yechunliang b11460f7f6 replace malloc and memset with calloc
malloc: allocate a block of memory, the contents of the block are undefined.
calloc: allocate a block of memory for an array of num elements and initializes all its bits to zero.

Signed-off-by: yechunliang <yechunliangcn@163.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi 92d86383be hv:check continuous hpa when create secure world
Add check_continuous_hpa API:
when create secure world,if the physical
address is not continuous, will assert.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi e5be957945 hv:add destroy Secure world API
This patch added API destroy_secure_world, which will do:
-- clear trusty memory space
-- restore memory to SOS ept mapping
It will be called when VM is destroyed, furthermore, ept of
Secure world will be destroyed as well.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Qi Yadong c83bcded99 trusty: fix typo of comments
Remove TODO comments since it has been done below the comments.
Typo fix: startup_info --> startup_param.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Minggui Cao 2db1324837 add vmx msr ops protection from guest OS
1.it doesn't support VMX for guest OS
2.for MSR out of control, inject GP to guest OS.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi 5e3dca4c0c hv: free ept memory enhancement
--add free_paging_struct api, used for free page tables
  it will clear memory before free.
--add HPA2HVA translation when free ept memory

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi cf7fe07276 hv:bugfix for the API of creating secure world
Before this patch, HV accesses PML4E of secure world when the PML4
doesn't exist,will access null pointer.
Fix as follow:
Before the copy of PDPTE,will allocate memory and write PML4E,
then copy the PDPTE.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Junjie Mao f347d15e7d hv: cpu: use the physical address limit from CPUID when available
Per SDM Vol. 2:

    If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
    number supported should come from this field.

This patch gets the maximum physical address number from CPUID leaf
0x80000008 and calculates the physical address mask when the leaf is
available.

Currently ACRN does not support platforms w/o this leaf and will panic
on such platforms.

Also call get_cpu_capabilities() earlier since the physical address mask
is required for initializing paging.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Junjie Mao cc975f7858 cpu: cache the maximum input value for CPUID extended function
Per SDM:

    When CPUID executes with EAX set to 80000000H, the processor returns
    the highest value the processor recognizes for returning extended
    processor information. The value is returned in the EAX register and is
    processor specific.

This patch caches this value in the global cpuinfo_x86.cpuid_leaves. This
value will be used to check the availability of any CPUID extended
function.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Minggui Cao 3f03dee3d5 enable TSC-offset & add TSC MSR emulation
enable TSC offset in VMX, so if TSC MSR is changed by guest OS,
write a caculated value into TSC-offset, then host TSC will not be changed.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: He, Min <min.he@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Yonghua Huang 316731c9a5 hv: pass-through xsave feature to guests
enable Xsave feature and pass-through it to guests
 update based on v2:
  - enable host xsave before expose it to guests.
  - add validation for the value to be set to 'xcr0' before call xsetbv
    when handling xsetbv vmexit.
  - tested in SOS guest, created two threads to do different
    FP calculations,test code runs in user land of sos.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Junjie Mao c01a236efb treewide: fix declarations of functions with empty parameter lists
According to C99:

    The empty list in a function declarator that is not part of a definition of
    that function specifies that no information about the number or types of the
    parameters is supplied.

This means gcc is happy with the following code, which is undesirable.

    void foo();    /* declaration with an empty parameter list */

    void bar() {
        foo();     /* OK */
        foo(1);    /* OK */
        foo(1, 2); /* OK */
    }

This patch fixes declarations of functions with empty parameter lists by adding
an unnamed parameter of type void, which is the standard way to specify that a
function has no parameters. The following coccinelle script is used.

    @@
    type T;
    identifier f;
    @@

    -T f();
    +T f(void);

New compilation errors are fixed accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Mingqiang Chi de5277fb3e hv: Save secure world memory info into vm instead of vm0
A bugfix for saving secure world memory info.
Maybe there are multiple UOS, each VM has its own secure
world and normal world, should save memory info into individual VM.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:19:39 +08:00
Rusty Lynch 80a7dda419 Fix compile error caused by missing memcpy function
On some toolchain configurations direct struct assignments will
default to a memcpy operation which is not present in this
environment, so explicitly use the internal memcpy_s function.

Signed-of-by: Rusty Lynch <rusty.lynch@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen fde0789ccc UEFI: change the efi_ctx passing method
Save the pointer of efi_ctx in mi_drivers_addr field of
multiboot structure and pass to hypervisor, not by
saving in register RDX(the third default parameter in
64bit call function).

With this method, we can be compatible with the original
32bit boot parameters passing method and no need to
large the array size of boot_regs in hypervisor.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong 8d67f292ef Rename TIME_MS_DELTA to CYCLES_PER_MS
TIME_MS_DELTA is not clear enough, rename it to CYCLES_PER_MS.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong 8502c8eff3 io: remove pio emulation restriction
Currently, the serial log is printed through IO(0x3f8).
Secure World will print serial log by port 0x3f8. So
remove the ASSERT for Secure World booting.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong 922daae198 trusty: add key_info for trusty bring-up
For trusty bring-up, key_info is needed.
Currently, bootloader did not transfer key_info to hypervisor.
So in this patch, use dummy key_info temporarily.

Derive vSeed from dSeed before trusty startup, the vSeed will
bind with UUID of each VM.

Remove key_info from sworld_control structure.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong b124e0da28 trusty: implement hypercall to initialize trusty
UOS_Loader will trigger boot of Trusty-OS by HC_INITIALIZE_TRUSTY.
UOS_Loader will load trusty image and alloc runtime memory for
trusty. UOS_Loader will transfer these information include
trusty runtime memory base address, entry address and memory
size to hypervisor by trusty_boot_param structure.

In hypervisor, once HC_INITIALIZE_TRUSTY received, it will create
EPT for Secure World, save Normal World vCPU context, init
Secure World vCPU context and switch World state to Secure World.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong 1fd07ba349 trusty: Simulate Secure Monitor Call(SMC) by Hypercall
For ARM, The SMC instruction is used to generate a synchronous
exception that is handled by Secure Monitor code running in EL3.
In the ARM architecture, synchronous control is transferred between
the normal Non-secure state and the Secure state through Secure
Monitor Call exceptions. SMC exceptions are generated by the SMC
instruction, and handled by the Secure Monitor.The operation of
the Secure Monitor is determined by the parameters that are passed
in through registers.

For ACRN, Hypervisor will simulate SMC by hypercall to switch vCPU
State between Normal World and Secure World.
There are 4 registers(RDI, RSI, RDX, RBX) reserved for paramters
passing between Normal World and Secure World.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ 4f40b53c73 ptdev: fix ptdev_hv_owned_intx under release version
for release version, the vuart is not be used - pin 4 then is not used
by hypervisor.
this patch adds check for vm0->vuart to distinguish it.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ c7dd6a51b5 Remove STATIC_ASSERT Macro and replace with standard _Static_assert
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:19:38 +08:00
Li, Fei1 5a47c267e3 hv: vlapic: simple vlapic_rd/wr input
Remove unnecessary input parameters

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:38 +08:00
Li, Fei1 57152d0f27 hv: lapic: export write_lapic_reg32
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ 471082cc6c ptdev: refine function input parameters
functions ptdev_build_physical_rte & activate_physical_ioapic
doesn't need to get parameters like phys_irq, ptdev_intx_info or vector
from caller, instead they can derive from entry.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ a8b377145e ptdev: refine the functions name & code position
refine some functions name and put functions under proper sequence
- get_remapping_entry -> get_entry
- ptdev_native_owned_intx -> ptdev_hv_owned_intx
- ptdev_build_native_msi -> ptdev_build_physical_msi
- ptdev_build_native_rte -> ptdev_build_physical_rte
- update_active_native_ioapic -> activate_physical_ioapic
- ptdev_vm_deinit -> ptdev_release_all_entries

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ 70d4dbace7 ptdev: change the ptdev_lock from per-vm to global
this patch is a preparation for changing ptdev remapping entry from
virtual to physical based, it changes the ptdev_lock from per-vm to
global, as entries based on physical mode are global resource.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Jason Chen CJ 9d02932ec4 ptdev: change the ptdev_list from per-vm to global
this patch is a preparation for changing ptdev remapping entry from
virtual to physical based, it changes the ptdev_list from per-vm to
global, as entries based on physical mode are global resource.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Li, Fei1 6c1122f869 cpuid restruct
Generate all common virtual cpuid entries for flexible support of
guest VCPUID emulation, by decoupling from PCPUID.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Chen, Jason CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:38 +08:00
Yin Fengwei 4073b37369 hv: microcode: Enable microcode update from SOS.
microcode update from UOS is disabled.
microcode version checking is available for both SOS and UOS.

There are two TODOs of this patch:
1. This patch only update the uCode on pCPUs SOS owned. For the
   pCPUs not owned by SOS, the uCode is not updated. To handle
   this gap, we will have SOS own all pCPUs at boot time. So
   all pCPUs could have uCode updated. This will be handled
   in the patch to enable SOS own all pCPUs at boot time.

2. gva2gpa now doesn't check possible page table walk failure.
   Will add the failure check in gva2gpa in different patch.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Anthony Xu (anthony.xu@intel.com)
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Tian, Kevin <kevin.tian@intel.com>
2018-05-15 17:19:37 +08:00
Li, Fei1 4110e25eae Add cpuinfo_x86 to cache cpu capability/feature
Add a global boot_cpu_data to cache common cpu capbility/feature
for detect cpu capbility/feature.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:19:37 +08:00
Jason Chen CJ 4839f780e4 ioreq: only clear vcpu->req when io request needed
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:37 +08:00
Li, Fei1 936c254d58 Don't use HV_DEBUG outside debug directory
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang d6904b412c hv: rename VM exit handlers in vlapic
to keep aligned with the vmexit reasons' name defined in
SPEC.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang 7d8803f5ea hv:enable APICv features based on CPU capability
this patch is to detect and enable only APICv features which
are actually supported by the processor, instead fo tuning on
all features by default.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang f01a8eef58 Add APIC ACCESS VMexit handler
Update 'apic_access_exit_handler()' function to emulate
guest instruments to read/write guest's lapic registers page

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang 9b269aee79 Add handle EOI case when APIC-write VM exit
-If "virtual-interrupt delivery" VM-execution control is 0,
  Processor will causes an APIC-write VM exit if page offset
  is 0xB0 (EOI), SDM Vol3, Chapter 29.4.3

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:37 +08:00
Jason Chen CJ fcb95d02d6 uefi: init vlapic according to native lapic
this patch save native lapic configuration and restore it to vm0's vlapic
before its running, then doing hpet timer interrupt injection through vlapic
interface -- this will not mess up vlapic and we can see hpet
timer interrupt coming continuously.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:37 +08:00
Jason Chen CJ a87757d602 uefi: remove old interrupt injection method
we added uefi stub for hv, and want vm0 continue running under uefi env to
boot other uefi payload (osloader or bzImage).

during this, the uefi timer irq need be handled elegantly.

there are 3 types for uefi timer:
1. 8254 based on IRQ0 of PIC
2. HPET based on IOAPIC
3. HPET based on MSI

currently, we only support type 3 (HPET+MSI). But we are following a
in-correct flow to handle this timer interrupt:
- we set VMX_ENTRY_INT_INFO_FIELD directly if a timer interrupt happened
  before vcpu launching, this will make its vlapic mess up, which finally
  cause hpet timer stop.

this patch remove this in-correct approach, the new approach patch will
be followed by next patch.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:37 +08:00
Mingqiang Chi 2deb4cb458 mmu: Rename several variables related to page table type
rename 'PT_HOST' to 'PTT_HOST'
rename 'PT_EPT' to 'PTT_EPT'
rename 'ept_type' to 'table_type'

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:37 +08:00
Zheng, Gen 124910ba14 vm load: fix bug in loading kernel
According to the explaination for pref_address
in Documentation/x86/boot.txt, a relocating bootloader
should attempt to load kernel at pref_address if possible.
But due to a non-relocatable kernel will unconditionally
move itself and to run at perf address, no need to copy
kernel to perf_address by bootloader.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:37 +08:00
Jason Chen CJ 155be81dbf ptdev: fix bug when update ptdev entry
info->phys_pin need be used by ptdev_build_native_rte when updating entry

TODO: currently ptdev entry is virtual based, the better solution should
be physical based.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:37 +08:00
Zhao Yakui fe9dfc7842 Jmp to vm_exit directly to avoid calling vmlaunch again if vm-entry fails in vmresume
It is possible that the vm-entry fails in vmresume instr under some scenarios.
It will pass to next instruction following vmresume. In such case it will call
the vmlaunch again.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2018-05-15 17:19:37 +08:00
Mingqiang Chi f4780c0cd4 Remove unnecessary variable in map_mem
the variable 'table_present' is redundant
in function(map_mem_region)

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:37 +08:00
Minggui Cao 119b038551 to support firmware & ramdisk as multiboot mods
1. refine multiboot related code, move to /boot.
2. firmware files and ramdisk can be stitched in iasImage;
and they will be loaded as multiboot modules.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
2018-05-15 17:19:37 +08:00
Mingqiang Chi 35f5eef658 Add page mask MACRO
Add 'CPU_PAGE_MASK' used for calculate address,
Change IA32E_REF_MASK from 0x7ffffffffffff000 to 0x000ffffffffff000
for MMU/EPT entry, bit62:52(ignore) bit63(VE/XD)
if we want to obtain the address from the MMU/EPT entry,need to clear
bit63:52 by IA32E_REF_MASK

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:37 +08:00
Yonghua Huang 83e78e16c7 align the coding style when access VMEXIT_QUAL
- align coding style to avoid redundant operations
   when operating on reading  VMX_EXIT_QUALIFICATION

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:19:36 +08:00
Li, Fei1 429302c72a minor fix on get_ptdev_info
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:36 +08:00
Mingqiang Chi c451f2e4fa add create secure world ept API
This patch is prepared for enabling secure world feature.
this api will create new eptp for secure world, whose PDPT
entries are copied form normal world,the PML4/PDPT for secure
world are separated from Normal World, PD/PT are shared in the
Secure World's EPT and Normal World's EPT.Secure world can
access Normal World's memory, but Normal World can not access
Secure World's memory
This function implemented:
-- Unmap specific memory from guest ept mapping
-- Copy PDPT from Normal world to Secure world
-- Map specific memory for Secure world
-- Unmap specific memory from SOS ept mapping

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:36 +08:00
Li, Fei1 74e2bfc15f Simple get_vmx_cap()
Don't check MSR Control Features in get_vmx_cap

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:36 +08:00
Li, Fei1 cc2256d3f6 Call monitor_cap_detect in bsp_boot_init
On the APL NUC board (CPU family: 0x6 model: 92), the monitor is buggy.
We can't use it to wake up CPU core from mwait by memory monitor.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:36 +08:00
Mingqiang Chi cc1d532131 add data structure in vm for enable trusty feature
add key info structure
add sworld_eptp in vm structure, and rename ept->nworld_eptp
add secure world control structure

Change-Id:
Tracked-On:220921
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ d14a7dbdd2 retpoline: add indirect thunk support
for gcc version > 7.3, enable CONFIG_RETPOLINE

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ c244e8b5a3 vpic: use calloc to init vpic instead of malloc
vpic struct should be init as 0

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ eed8104f69 uefi: restore cr registers according to efi context
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:36 +08:00
Yin Fengwei 189329e0de apicv: cancel event injection if vcpu is scheduled out
And re-inject the event after vcpu is scheduled in.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ 2cb8ce50c1 decouple hv sw version and api version
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-11 14:44:29 +08:00
Eddie Dong 7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00