hv: cpu: add cpu_has_cap() API
Add cpu_has_cap API for cpu feature/capability detect instead of add get_xxx_cap for each feature/capability detect. Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li, Fei1
Jack Ren
parent
bb011a4316
commit
6560ff367c
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@ -94,25 +94,20 @@ static void start_cpus(void);
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static void pcpu_sync_sleep(unsigned long *sync, int mask_bit);
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int ibrs_type;
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static inline bool get_tsc_adjust_cap(void)
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inline bool cpu_has_cap(uint32_t bit)
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{
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return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EBX] & CPUID_EBX_TSC_ADJ);
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}
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int feat_idx = bit >> 5;
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int feat_bit = bit & 0x1f;
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static inline bool get_ibrs_ibpb_cap(void)
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{
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return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX] &
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CPUID_EDX_IBRS_IBPB);
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}
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if (feat_idx >= FEATURE_WORDS)
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return false;
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static inline bool get_stibp_cap(void)
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{
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return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX] & CPUID_EDX_STIBP);
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return !!(boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit));
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}
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static inline bool get_monitor_cap(void)
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{
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if (boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_MONITOR) {
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if (cpu_has_cap(X86_FEATURE_MONITOR)) {
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/* don't use monitor for CPU (family: 0x6 model: 0x5c)
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* in hypervisor, but still expose it to the guests and
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* let them handle it correctly
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@ -124,11 +119,6 @@ static inline bool get_monitor_cap(void)
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return false;
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}
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inline bool get_vmx_cap(void)
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{
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return !!(boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_VMX);
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}
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static uint64_t get_address_mask(uint8_t limit)
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{
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return ((1ULL << limit) - 1) & CPU_PAGE_MASK;
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@ -198,9 +188,9 @@ static void get_cpu_capabilities(void)
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* should be set all the time instead of relying on retpoline
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*/
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#ifndef CONFIG_RETPOLINE
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if (get_ibrs_ibpb_cap()) {
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if (cpu_has_cap(X86_FEATURE_IBRS_IBPB)) {
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ibrs_type = IBRS_RAW;
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if (get_stibp_cap())
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if (cpu_has_cap(X86_FEATURE_STIBP))
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ibrs_type = IBRS_OPT;
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}
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#endif
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@ -470,7 +460,8 @@ void bsp_boot_init(void)
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pr_dbg("Core %d is up", CPU_BOOT_ID);
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/* Warn for security feature not ready */
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if (!get_ibrs_ibpb_cap() && !get_stibp_cap()) {
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if (!cpu_has_cap(X86_FEATURE_IBRS_IBPB) &&
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!cpu_has_cap(X86_FEATURE_STIBP)) {
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pr_fatal("SECURITY WARNING!!!!!!");
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pr_fatal("Please apply the latest CPU uCode patch!");
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}
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@ -786,7 +777,7 @@ static void cpu_xsave_init(void)
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{
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uint64_t val64;
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if (is_xsave_supported()) {
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if (cpu_has_cap(X86_FEATURE_XSAVE)) {
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CPU_CR_READ(cr4, &val64);
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val64 |= CR4_OSXSAVE;
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CPU_CR_WRITE(cr4, val64);
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@ -152,7 +152,7 @@ int hv_main(int cpu_id)
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"cpu_id/tsc_aux mismatch");
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/* Check if virtualization extensions are supported */
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ret = get_vmx_cap();
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ret = cpu_has_cap(X86_FEATURE_VMX);
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ASSERT(ret == 1, "VMX not supported!");
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/* Enable virtualization extensions */
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@ -224,15 +224,15 @@ extern uint64_t pcpu_active_bitmap;
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/* CPUID feature words */
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enum feature_word {
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FEAT_1_ECX, /* CPUID[1].ECX */
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FEAT_1_EDX, /* CPUID[1].EDX */
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FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
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FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
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FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
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FEAT_8000_0000_EAX, /* CPUID[8000_0000].EAX */
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FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
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FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
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FEAT_8000_0008_EAX, /* CPUID[8000_0008].EAX */
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FEAT_1_ECX = 0, /* CPUID[1].ECX */
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FEAT_1_EDX = 1, /* CPUID[1].EDX */
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FEAT_7_0_EBX = 2, /* CPUID[EAX=7,ECX=0].EBX */
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FEAT_7_0_ECX = 3, /* CPUID[EAX=7,ECX=0].ECX */
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FEAT_7_0_EDX = 4, /* CPUID[EAX=7,ECX=0].EDX */
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FEAT_8000_0000_EAX = 5, /* CPUID[8000_0000].EAX */
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FEAT_8000_0001_ECX = 6, /* CPUID[8000_0001].ECX */
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FEAT_8000_0001_EDX = 7, /* CPUID[8000_0001].EDX */
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FEAT_8000_0008_EAX = 8, /* CPUID[8000_0008].EAX */
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FEATURE_WORDS,
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};
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@ -258,8 +258,8 @@ int hv_main(int cpu_id);
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bool is_vapic_supported(void);
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bool is_vapic_intr_delivery_supported(void);
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bool is_vapic_virt_reg_supported(void);
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bool get_vmx_cap(void);
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bool is_xsave_supported(void);
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bool cpu_has_cap(uint32_t bit);
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/* Read control register */
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#define CPU_CR_READ(cr, result_ptr) \
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@ -0,0 +1,105 @@
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/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __X86_CPUFEATURES_H__
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#define __X86_CPUFEATURES_H__
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/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
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#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0)
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#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1)
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#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2)
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#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3)
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#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4)
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#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5)
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#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6)
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#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7)
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#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8)
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#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9)
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#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10)
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#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12)
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#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13)
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#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14)
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#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15)
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#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17)
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#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18)
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#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19)
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#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20)
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#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21)
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#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22)
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#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23)
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#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25)
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#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26)
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#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27)
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#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28)
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/* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/
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#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0)
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#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1)
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#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2)
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#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3)
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#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4)
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#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5)
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#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6)
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#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7)
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#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8)
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#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9)
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#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11)
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#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12)
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#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13)
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#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14)
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#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15)
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#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16)
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#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17)
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#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18)
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#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19)
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#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21)
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#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22)
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#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23)
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#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24)
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#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25)
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#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26)
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#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27)
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#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28)
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#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29)
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#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30)
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#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
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#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1)
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#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
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#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26)
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#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27)
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/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/
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#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26)
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#endif /*__X86_CPUFEATURES_H__*/
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@ -58,5 +58,6 @@
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#include <vioapic.h>
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#include <guest.h>
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#include <vmexit.h>
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#include <cpufeatures.h>
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#endif /* HV_ARCH_H */
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