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acrn-hypervisor
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Revert "HV: Prepare cpu_secondary.S for AP trampoline code relocation" 

This reverts commit bfa67fa6a0.
This commit is contained in:
lijinxia 2018-05-09 10:28:17 +00:00 committed by Jack Ren
parent b3dd135ed3
commit 3b6fe5782d
4 changed files with 16 additions and 25 deletions
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36
hypervisor/arch/x86/cpu_secondary.S
View File

@ -46,7 +46,6 @@
.align 4
.code16
.global cpu_secondary_reset
.org 0
cpu_secondary_reset:
/* Disable local interrupts */
@ -62,9 +61,8 @@ cpu_secondary_reset:
/* Set CR3 to PML4 table address */
movl $CPU_Boot_Page_Tables_ptr, %ebx
mov (%ebx), %eax
mov %eax, %cr3
movl $CPU_Boot_Page_Tables_Start, %edi
mov %edi, %cr3
/* Set LME bit in EFER */
@ -85,14 +83,7 @@ cpu_secondary_reset:
/* Perform a long jump based to start executing in 64-bit mode */
movl $ap_long_mode_jump_ref, %ebx
ljmpl *(%ebx)
.align 8
.global ap_long_mode_jump_ref
ap_long_mode_jump_ref:
.long cpu_secondary_long_mode
.word HOST_GDT_RING0_CODE_SEL
data32 ljmp $HOST_GDT_RING0_CODE_SEL, $cpu_secondary_long_mode
.code64
cpu_secondary_long_mode:
@ -109,8 +100,7 @@ cpu_secondary_long_mode:
/* Obtain secondary CPU spin-lock to serialize
booting of secondary cores for a bit */
mov $cpu_secondary_spinlock, %rdi
spinlock_obtain(%rdi)
spinlock_obtain(cpu_secondary_spinlock)
/* Initialize temporary stack pointer
NOTE: Using the PML4 memory (PDPT address is top of memory
@ -120,15 +110,21 @@ cpu_secondary_long_mode:
the top of this page. This stack is only
used for a VERY short period of time, so
this reuse of PML4 memory should be acceptable. */
lea cpu_secondary_pdpt_addr(%rip), %rsp
movq $cpu_secondary_pdpt_addr, %rsp
/* Push sp magic to top of stack for call trace */
pushq $SP_BOTTOM_MAGIC
/* Jump to C entry for the AP */
mov $cpu_secondary_init, %rax
jmp *%rax
call cpu_secondary_init
cpu_secondary_error:
/* Error condition trap */
jmp cpu_secondary_error
/* GDT table */
.align 4
@ -140,23 +136,17 @@ cpu_secondary_gdt_end:
/* GDT pointer */
.align 2
.global cpu_secondary_gdt_ptr
cpu_secondary_gdt_ptr:
.short (cpu_secondary_gdt_end - cpu_secondary_gdt) - 1
.quad cpu_secondary_gdt
/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
.align 4
.global CPU_Boot_Page_Tables_ptr
CPU_Boot_Page_Tables_ptr:
.long CPU_Boot_Page_Tables_Start
.align CPU_PAGE_SIZE
.global CPU_Boot_Page_Tables_Start
CPU_Boot_Page_Tables_Start:
.quad cpu_secondary_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
.align CPU_PAGE_SIZE
.global cpu_secondary_pdpt_addr
cpu_secondary_pdpt_addr:
address = 0
.rept 4

3
hypervisor/bsp/ld/link_ram.ld.in
View File

@ -5,7 +5,7 @@ ENTRY(cpu_primary_start_32)
MEMORY
{
/* Low 1MB of memory for secondary processor start-up */
lowram : ORIGIN = 0, LENGTH = CONFIG_LOW_RAM_SIZE
lowram : ORIGIN = CONFIG_LOW_RAM_START, LENGTH = CONFIG_LOW_RAM_SIZE
/* 32 MBytes of RAM for HV */
ram : ORIGIN = CONFIG_RAM_START, LENGTH = CONFIG_RAM_SIZE
@ -43,7 +43,6 @@ SECTIONS
.cpu_secondary : AT (_ld_cpu_secondary_reset_load)
{
/* entry point of AP wakeup, must be at the beginning of this section*/
_ld_cpu_secondary_reset_start = .;
*(.cpu_secondary_reset);
. = ALIGN(4);

1
hypervisor/bsp/sbl/include/bsp/bsp_cfg.h
View File

@ -41,6 +41,7 @@
#define HEAP_SIZE 0x100000
#define CONSOLE_LOGLEVEL_DEFAULT 2
#define MEM_LOGLEVEL_DEFAULT 4
#define CONFIG_LOW_RAM_START 0x00001000
#define CONFIG_LOW_RAM_SIZE 0x000CF000
#define CONFIG_RAM_START 0x6E000000
#define CONFIG_RAM_SIZE 0x02000000 /* 32M */

1
hypervisor/bsp/uefi/include/bsp/bsp_cfg.h
View File

@ -41,6 +41,7 @@
#define HEAP_SIZE 0x100000
#define CONSOLE_LOGLEVEL_DEFAULT 2
#define MEM_LOGLEVEL_DEFAULT 4
#define CONFIG_LOW_RAM_START 0x00008000
#define CONFIG_LOW_RAM_SIZE 0x00010000
#define CONFIG_RAM_START 0x20000000
#define CONFIG_RAM_SIZE 0x02000000 /* 32M */