hv: refine the left atomic operation
rename atomic_cmpxchg_int to atomic_cmpxchg replace atomic_cmpset_long with atomic_cmpxchg64 rename atomic_readandclear_long to atomic_readandclear64 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Li, Fei1
lijinxia
parent
1f3da93e74
commit
edb26a7e17
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@ -1992,7 +1992,7 @@ apicv_set_intr_ready(struct vlapic *vlapic, int vector, __unused bool level)
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mask = 1UL << (vector % 64);
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atomic_set_long(&pir_desc->pir[idx], mask);
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notify = atomic_cmpset_long(&pir_desc->pending, 0, 1);
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notify = (atomic_cmpxchg64((long *)&pir_desc->pending, 0, 1) == 0);
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return notify;
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}
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@ -2109,7 +2109,7 @@ apicv_inject_pir(struct vlapic *vlapic)
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struct lapic_reg *irr = NULL;
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pir_desc = vlapic->pir_desc;
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if (atomic_cmpset_long(&pir_desc->pending, 1, 0) == 0)
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if (atomic_cmpxchg64((long *)&pir_desc->pending, 1, 0) != 1)
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return;
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pirval = 0;
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@ -2118,7 +2118,7 @@ apicv_inject_pir(struct vlapic *vlapic)
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irr = &lapic->irr[0];
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for (i = 0; i < 4; i++) {
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val = atomic_readandclear_long(&pir_desc->pir[i]);
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val = atomic_readandclear64((long *)&pir_desc->pir[i]);
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if (val != 0) {
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irr[i * 2].val |= val;
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irr[(i * 2) + 1].val |= val >> 32;
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@ -179,7 +179,7 @@ static int uart16550_open(struct tgt_uart *tgt_uart,
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int status = 0;
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if (strcmp(tgt_uart->uart_id, "STDIO") == 0) {
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if (atomic_cmpxchg_int(&tgt_uart->open_count, 0, 1) != 0)
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if (atomic_cmpxchg(&tgt_uart->open_count, 0, 1) != 0)
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return -EBUSY;
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/* Call UART setup function */
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@ -264,7 +264,7 @@ static int uart16550_get_rx_err(uint32_t rx_data)
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static void uart16550_close(struct tgt_uart *tgt_uart)
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{
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if (tgt_uart != NULL) {
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if (atomic_cmpxchg_int(&tgt_uart->open_count, 1, 0) == 1) {
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if (atomic_cmpxchg(&tgt_uart->open_count, 1, 0) == 1) {
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/* TODO: Add logic to disable the UART */
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}
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}
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@ -56,6 +56,26 @@ static inline void name(volatile type *ptr, type v) \
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build_atomic_store(atomic_store, "l", int, p, v)
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build_atomic_store(atomic_store64, "q", long, p, v)
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#define build_atomic_inc(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "inc" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_inc(atomic_inc, "l", int, p)
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build_atomic_inc(atomic_inc64, "q", long, p)
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#define build_atomic_dec(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "dec" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_dec(atomic_dec, "l", int, p)
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build_atomic_dec(atomic_dec64, "q", long, p)
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/*
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* #define atomic_set_int(P, V) (*(unsigned int *)(P) |= (V))
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*/
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@ -78,46 +98,6 @@ static inline void atomic_clear_int(unsigned int *p, unsigned int v)
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: "cc", "memory");
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}
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#define build_atomic_inc(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "inc" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_inc(atomic_inc, "l", int, p)
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build_atomic_inc(atomic_inc64, "q", long, p)
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#define build_atomic_dec(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "dec" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_dec(atomic_dec, "l", int, p)
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build_atomic_dec(atomic_dec64, "q", long, p)
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/*
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* #define atomic_swap_int(P, V) \
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* (return (*(unsigned int *)(P)); *(unsigned int *)(P) = (V);)
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*/
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static inline int atomic_swap_int(unsigned int *p, unsigned int v)
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{
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__asm __volatile(BUS_LOCK "xchgl %1,%0"
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: "+m" (*p), "+r" (v)
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:
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: "cc", "memory");
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return v;
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}
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/*
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* #define atomic_readandclear_int(P) \
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* (return (*(unsigned int *)(P)); *(unsigned int *)(P) = 0;)
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*/
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#define atomic_readandclear_int(p) atomic_swap_int(p, 0)
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/*
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* #define atomic_set_long(P, V) (*(unsigned long *)(P) |= (V))
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*/
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@ -140,37 +120,43 @@ static inline void atomic_clear_long(unsigned long *p, unsigned long v)
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: "cc", "memory");
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}
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/*
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* #define atomic_swap_long(P, V) \
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* (return (*(unsigned long *)(P)); *(unsigned long *)(P) = (V);)
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*/
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static inline long atomic_swap_long(unsigned long *p, unsigned long v)
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{
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__asm __volatile(BUS_LOCK "xchgq %1,%0"
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: "+m" (*p), "+r" (v)
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:
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: "cc", "memory");
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return v;
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#define build_atomic_swap(name, size, type, ptr, v) \
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static inline type name(type *ptr, type v) \
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{ \
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asm volatile(BUS_LOCK "xchg" size " %1,%0" \
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: "+m" (*ptr), "+r" (v) \
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: \
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: "cc", "memory"); \
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return v; \
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}
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build_atomic_swap(atomic_swap, "l", int, p, v)
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build_atomic_swap(atomic_swap64, "q", long, p, v)
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/*
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* #define atomic_readandclear_long(P) \
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* (return (*(unsigned long *)(P)); *(unsigned long *)(P) = 0;)
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*/
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#define atomic_readandclear_long(p) atomic_swap_long(p, 0)
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/*
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* #define atomic_readandclear(P) \
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* (return (*(int *)(P)); *(int *)(P) = 0;)
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*/
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#define atomic_readandclear(p) atomic_swap(p, 0)
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static inline int atomic_cmpxchg_int(unsigned int *p,
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int old, int new)
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{
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int ret;
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/*
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* #define atomic_readandclear64(P) \
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* (return (*(long *)(P)); *(long *)(P) = 0;)
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*/
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#define atomic_readandclear64(p) atomic_swap64(p, 0)
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__asm __volatile(BUS_LOCK "cmpxchgl %2,%1"
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: "=a" (ret), "+m" (*p)
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: "r" (new), "0" (old)
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: "memory");
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return ret;
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#define build_atomic_cmpxchg(name, size, type, ptr, old, new) \
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static inline type name(volatile type *ptr, \
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type old, type new) \
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{ \
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type ret; \
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asm volatile(BUS_LOCK "cmpxchg" size " %2,%1" \
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: "=a" (ret), "+m" (*p) \
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: "r" (new), "0" (old) \
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: "memory"); \
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return ret; \
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}
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build_atomic_cmpxchg(atomic_cmpxchg, "l", int, p, old, new)
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build_atomic_cmpxchg(atomic_cmpxchg64, "q", long, p, old, new)
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#define build_atomic_xadd(name, size, type, ptr, v) \
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static inline type name(type *ptr, type v) \
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@ -196,17 +182,4 @@ build_atomic_xadd(atomic_xadd64, "q", long, p, v)
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#define atomic_inc64_return(v) atomic_add64_return((v), 1)
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#define atomic_dec64_return(v) atomic_sub64_return((v), 1)
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static inline int
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atomic_cmpset_long(unsigned long *dst, unsigned long expect, unsigned long src)
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{
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unsigned char res;
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__asm __volatile(BUS_LOCK "cmpxchg %3,%1\n\tsete %0"
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: "=q" (res), "+m" (*dst), "+a" (expect)
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: "r" (src)
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: "memory", "cc");
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return res;
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}
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#endif /* ATOMIC_H*/
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