Linux reported incorrect MTRR mask programming in SBL. This patch
fixed this issue by using the proper MTRR mask for GFX FB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Currently, the 1st time stamp includes FSP-T execution time in X64.
This will read the 1st time stamp before TempRamInit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.
X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Certain platforms can't support GpioLockUnlock, so let
them return the Opcode they want to use for locking.
Also updated dependent platform.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch changed QEMU FSP to use INF file to provide commit id.
It also synced up to the latest EDK2 stable tag edk2-stable202011.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Resolved yocto hang issue after booted into OS
for non Fusa sku.
Enabled s0ix for yocto and windows.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch adds support to build CSME firmware update driver.
BUILD_CSME_UPDATE_DRIVER in BoardConfig.py must set 1 to build csme FWU
driver.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
There is request to utilize MP in OsLoader. To support it, it is
desired to delay MP init done signal to the end of the OsLoader.
This patch moved the MP init done signal into board ReadyToBoot
notification so that MP is still alive in OsLoader phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In some cases Bootloader will build GFX HOB. This patch updated
SBL to check the bootloader GFX HOB first before building a new
GFX HOB from FSP. This is to avoid duplicated GFX HOB to be
generated in bootloader HOB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed a failure in firmware update that
occur during SBL version check. Current code assume
that the SBL layout does not change between the existing
firmware and the capsule, when the layout change, stage1A
address change and this is causing error while obtaining
the firmware version.
Code is modified to use the last 4 bytes of the SBL region
which contain Stage1A FV address and this is used to obtain
the version information.
Signed-off-by: Raghava <raghava.gudla@intel.com>
during CSME firmware update process, CSME update library throw error
"Could not access PCI device".this patch fixes this issue by adding
back "PciReadBuffer".
TEST=Verified CSME FWU on CFL-H & WHL platforms.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
This introduces an additional PCI Enumeration option.
- self._PCI_ENUM_FLAG_ALLOC_PMEM_FIRST
By deafult, the option will allocate PCI resource by ascending order
(MEM32->PMEM32->MEM64->PMEM64). If it's set to 1, by reversed order.
Signed-off-by: Aiden Park <aiden.park@intel.com>
The RegionPermission doesn't usually represent the current state of
the Region. There is a need to re-read the permission bit for each
read/write. There by making the variable accurately represents the
HW status.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
In some cases FSP does not support GFX and does not produce
GFX hob. But platform will be able to initialize its GFX after
PCI enumeration. This patch allows splash to be displayed post
PCI if the splash has not been displayed yet.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Point TGL project to use common GpioLib and fix build errors.
GpioPlatformLib instance for TGL platform is also provided
as a reference for other platforms. Also remove TGL specific
Gpio Library related files.
Usage:
To configure Gpio pins provided by GPIO CFG DATA:
ConfigureGpio(Gpio_Cfg_Data_Tag, 0, NULL);
To configure Gpio pins provided by GPIO_INIT_CONFIG array:
ConfigureGpio(0, Num_entries, Ptr_to_Array);
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This adds a common IgdOpRegion library for the same APIs on TGL
and EHL platforms. Plan to include older platforms support in the v2
patch.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
This patches fixes the audio record issue using onboard 3mm jack.
TEST= booted to windows on both CFL-S & CFL-H board and verified
Audio playback and record is working using onboard 3mm jack.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
similar to CML, CFL also uses both IOB2 & IOB3 ports to pass the info
and generate an SMI. where as common code ACPI implementation uses
only IOB2, hence TPM2 ACPI tables are ported from CML platforms.
This patch fixes physical presence query and TPM clear issue on windows.
TEST: boot to windows on CFL-H platform and verified TPM physical
presence and TPM clear command is successfull.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
This patch fixed a failure occured during CSME firmware
update. CSME firmware update library expects PCI read buffer
with a specific format, there is mismatch with input and output
parameter with the current code. Added a wrapper function
with the expected format to fix the failure.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current PCI resource PCD bases are defined as fixed type. It
makes it impossible to dynamically adjust the base at runtime.
This patch changed it to be module patchable so that platform
can update when required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add SBL configuration data for TCC GPIO.
Update TCC GPIO UPD and ACPI NVS data based
on SBL configuration data.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch moves the Linux build environment into latest Ubuntu
20.04 and updated to use latest ACPICA. All GCC build now is
enabled.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will fix invalid PDP/PDE generation with PAE 2MB Pages,
and high bit calculation at PayloadEntry additionally.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch enabled auto build for TGL Azure Pipelines.
Only Windows build is enabled. GCC build has IASL issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
1. Disable EISS if BLE is not set in DisableBiosWriteProtect()
2. Enable EISS if BLE is not set in EnableBiosWriteProtect()
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
To ease the process of configuring CFG settings to
enable TCC mode, 2 additional DLT files have been
added for TGL-U DDR4 & LPDDR4 boards that can be
copied over the default files (or updated in the
BoardConfig.py) to set TCC mode settings. There
are 2 expectations currently (subject to change
later on):
1. UEFI PLD will be used
2. NVMe media is used for capsule update location
Also, remove TGL-H DLT file since it is not used
currently and update BoardConfig.py accordingly.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
CFL, CML, EHL, TGL platforms are using PSD version 0.3.
as per PSD Spec v0.3 secureboot status indication as ber below,
000 – Secure boot is Disabled
001 – UEFI Secure boot is enabled
010 – Boot Guard is Enabled
100 – Bootloader Verified boot is Enabled
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
In 32 bit SBL, when PCI PMEM64 exists, the OsLoader will hang
during boot in CreateIdentityMappingPageTables(). The function
is inteneded to be used in X64 mode only, and cannot handle
32bit well. So OsLoader should not call it for 32 bit build.
This patch also zeroed the allcated memory to ensure the unused
entries are all 0.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will allow inherited BoardConfig from the existing one
in the same BoardPkg. It will be useful when a new BoardConfig
has very minimum difference from the existing one.
See Platform/QemuBoardPkg/BoardConfigOverride.py as a reference.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Maurice Ma