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Add silicon common IgdOpRegion library 

This adds a common IgdOpRegion library for the same APIs on TGL
and EHL platforms. Plan to include older platforms support in the v2
patch.

Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
This commit is contained in:
leanshen 2021-01-23 05:36:32 +08:00 committed by Maurice Ma
parent d988a8cc81
commit cf6663c996
16 changed files with 129 additions and 364 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
BootloaderCorePkg/BootloaderCorePkg.dec
View File

@ -159,6 +159,7 @@
gPlatformModuleTokenSpaceGuid.PcdAcpiTablesAddress | 0xFF000000 | UINT32 | 0x20000110
gPlatformModuleTokenSpaceGuid.PcdAcpiGnvsAddress | 0xFF000000 | UINT32 | 0x20000112
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress | 0xFF000000 | UINT32 | 0x20000113
gPlatformModuleTokenSpaceGuid.PcdIgdOpRegionAddress | 0xFF000000 | UINT32 | 0x20000114
gPlatformModuleTokenSpaceGuid.PcdSmramTsegBase | 0xFF000000 | UINT32 | 0x20000120
gPlatformModuleTokenSpaceGuid.PcdSmramTsegSize | 0x00000000 | UINT32 | 0x20000121
gPlatformModuleTokenSpaceGuid.PcdHashStoreBase | 0xFF000000 | UINT32 | 0x20000181

1
BootloaderCorePkg/BootloaderCorePkg.dsc
View File

@ -255,6 +255,7 @@
gPlatformModuleTokenSpaceGuid.PcdAcpiTablesAddress | 0xFF000000
gPlatformModuleTokenSpaceGuid.PcdAcpiGnvsAddress | 0xFF000000
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress| 0xFF000000
gPlatformModuleTokenSpaceGuid.PcdIgdOpRegionAddress| 0xFF000000
gPlatformModuleTokenSpaceGuid.PcdDeviceTreeBase | 0xFF000000
gPlatformCommonLibTokenSpaceGuid.PcdAcpiPmTimerBase | $(ACPI_PM_TIMER_BASE)
gPlatformModuleTokenSpaceGuid.PcdFSPSBase | $(FSP_S_BASE)

2
Platform/ElkhartlakeBoardPkg/BoardConfig.py
View File

@ -195,7 +195,7 @@ class Board(BaseBoard):
'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
'IgdOpRegionLib|Silicon/$(SILICON_PKG_NAME)/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
'BdatLib|Silicon/$(SILICON_PKG_NAME)/Library/BdatLib/BdatLib.inf',
'PchSciLib|Silicon/$(SILICON_PKG_NAME)/Library/PchSciLib/PchSciLib.inf',

38
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -705,6 +705,26 @@ UpdatePayloadId (
}
}
//Initialize Platform Igd OpRegion
VOID
EFIAPI
IgdOpRegionPlatformInit (
VOID
)
{
GLOBAL_NVS_AREA *Gnvs;
EFI_STATUS Status;
Gnvs = (GLOBAL_NVS_AREA *)(UINTN)PcdGet32 (PcdAcpiGnvsAddress);
Status = IgdOpRegionInit (NULL);
Gnvs->SaNvs.IgdOpRegionAddress = (UINT32)(UINTN)PcdGet32 (PcdIgdOpRegionAddress);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "VBT not found %r\n", Status));
}
}
/**
Do board specific init based on phase indication
@ -771,19 +791,11 @@ BoardInit (
break;
case PrePayloadLoading:
Status = IgdOpRegionInit ();
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "VBT not found %r\n", Status));
}
//
// Set SMMBASE_INFO dummy structure in TSEG before others
//
//
// Set REG_INFO struct in TSEG region except 'Val' for regs
//
#if 0
RetrieveMBPData ();
#endif
///
/// Initialize the IGD OpRegion
///
IgdOpRegionPlatformInit ();
///
/// Initialize the HECI device
///

1
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
View File

@ -70,6 +70,7 @@
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress
gPlatformModuleTokenSpaceGuid.PcdIgdOpRegionAddress
gPlatformCommonLibTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds
gPlatformCommonLibTokenSpaceGuid.PcdSpiIasImageRegionType
gPlatformCommonLibTokenSpaceGuid.PcdSpiIasImage1RegionSize

2
Platform/TigerlakeBoardPkg/BoardConfig.py
View File

@ -215,7 +215,7 @@ class Board(BaseBoard):
'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
'IgdOpRegionLib|Silicon/$(SILICON_PKG_NAME)/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
'HeciInitLib|Silicon/$(PCH_PKG_NAME)/Library/HeciInitLib/HeciInitLib.inf',
'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
'BdatLib|Silicon/$(SILICON_PKG_NAME)/Library/BdatLib/BdatLib.inf',

57
Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2008 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2008 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -981,6 +981,40 @@ TglULpDdr4GopVbtSpecificUpdate(
ChildStructPtr[2]->DeviceClass = NO_DEVICE;
}
//Initialize Platform Igd OpRegion
VOID
EFIAPI
IgdOpRegionPlatformInit (
VOID
)
{
GLOBAL_NVS_AREA *Gnvs;
IGD_OP_PLATFORM_INFO IgdPlatformInfo;
EFI_STATUS Status;
Gnvs = (GLOBAL_NVS_AREA *)(UINTN)PcdGet32 (PcdAcpiGnvsAddress);
IgdPlatformInfo.TurboIMON = Gnvs->SaNvs.GfxTurboIMON;
switch (GetPlatformId ()) {
case BoardIdTglUDdr4:
IgdPlatformInfo.callback = (GOP_VBT_UPDATE_CALLBACK)(UINTN)&TglUDdr4GopVbtSpecificUpdate;
break;
case BoardIdTglULp4Type4:
IgdPlatformInfo.callback = (GOP_VBT_UPDATE_CALLBACK)(UINTN)&TglULpDdr4GopVbtSpecificUpdate;
break;
default:
DEBUG((DEBUG_INFO, "Unsupported board Id %x .....\n", GetPlatformId ()));
IgdPlatformInfo.callback = NULL;
break;
}
Status = IgdOpRegionInit (&IgdPlatformInfo);
Gnvs->SaNvs.IgdOpRegionAddress = (UINT32)(UINTN)PcdGet32 (PcdIgdOpRegionAddress);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "VBT not found %r\n", Status));
}
}
/**
Do board specific init based on phase indication
@ -1003,7 +1037,6 @@ BoardInit (
SILICON_CFG_DATA *SiCfgData;
UINTN LpcBase;
BL_SW_SMI_INFO *BlSwSmiInfo;
GOP_VBT_UPDATE_CALLBACK VbtCallback;
switch (InitPhase) {
case PreSiliconInit:
@ -1086,25 +1119,7 @@ BoardInit (
break;
case PrePayloadLoading:
switch (GetPlatformId ()) {
case BoardIdTglUDdr4:
VbtCallback = (GOP_VBT_UPDATE_CALLBACK)(UINTN)&TglUDdr4GopVbtSpecificUpdate;
break;
case BoardIdTglULp4Type4:
VbtCallback = (GOP_VBT_UPDATE_CALLBACK)(UINTN)&TglULpDdr4GopVbtSpecificUpdate;
break;
default:
DEBUG((DEBUG_INFO, "Unsupported board Id %x .....\n", GetPlatformId ()));
VbtCallback = NULL;
break;
}
Status = IgdOpRegionInit (VbtCallback);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "VBT not found %r\n", Status));
}
#if 0
RetrieveMBPData ();
#endif
IgdOpRegionPlatformInit ();
///
/// Initialize the HECI device (for test HeciInitLib only)

1
Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
View File

@ -77,6 +77,7 @@
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress
gPlatformModuleTokenSpaceGuid.PcdIgdOpRegionAddress
gPlatformCommonLibTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds
gPlatformCommonLibTokenSpaceGuid.PcdSpiIasImageRegionType
gPlatformCommonLibTokenSpaceGuid.PcdSpiIasImage1RegionSize

8
Silicon/TigerlakePkg/Include/Library/IgdOpRegionLib.h → Silicon/CommonSocPkg/Include/Library/IgdOpRegionLib.h
View File

@ -11,7 +11,7 @@
VBT: Video BIOS Table (OEM customizable data)
IPU: Image Processing Unit
Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -286,6 +286,10 @@ VOID
IN CHILD_STRUCT **ChildStructPtr
);
typedef struct {
UINT8 TurboIMON;
GOP_VBT_UPDATE_CALLBACK callback;
} IGD_OP_PLATFORM_INFO;
/**
@ -300,7 +304,7 @@ VOID
EFI_STATUS
EFIAPI
IgdOpRegionInit (
IN GOP_VBT_UPDATE_CALLBACK GopVbtUpdateCallback
IN IGD_OP_PLATFORM_INFO *PlatformInfo
);
#endif

37
Silicon/TigerlakePkg/Library/IgdOpRegionLib/GopConfigLib.h → Silicon/CommonSocPkg/Library/IgdOpRegionLib/GopConfigLib.h
View File

@ -1,7 +1,7 @@
/** @file
Header file for GOP Configuration Library
Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -1095,6 +1095,31 @@ typedef struct {
} LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile
} BLOCK44_ALS;
/**
This defines the structure of Black Frame Insertion table entry.
**/
typedef struct {
/**
BFI Features\n
Bit[7-2] : Reserved\n
Bit[1] : Enable Brightness control in CUI\n
Bit[0] : Enable BFI in driver
**/
UINT8 EnableBits;
UINT8 BrightnessNonBFI; ///< Brightness percentage in non BFI mode
} BFI;
/**
This defines the structure of Block 45 (Black Frame insertion Support for LFP)
**/
typedef struct {
UINT8 BlockId; ///< Defines the unique Block ID : 45
UINT16 BlockSize; ///< Defines the size of Black frame insertion support block.
UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of black frame data.
BFI BFI_Struct[16]; ///< Array defining the data of black frame insertion for all 16 panels.
} BLOCK45_BFI_SUPPORT;
/**
This structure defines the chromaticity information for a single LFP panel.
**/
@ -1432,6 +1457,16 @@ typedef struct {
UINT8 PmicI2cBusNo[6];
} BLOCK52_MIPI_CONF;
/**
This defines the structure of Block 53 (MIPI Sequence block) for panel initialisation.
**/
typedef struct {
UINT8 BlockId; ///< Defines the unique Block ID: 53
UINT16 BlockSize; ///< Defines the size of MIPI sequence Block
UINT8 Version; ///< Defines the version of MIPI sequence.
UINT8* MipiSequence; ///< Pointer to the actual MIPI sequence structure.
} BLOCK53_MIPI_SEQ;
/**
This defines the structure of a single RGB Palette entry block
for programming Gamma, Brightness, Contrast.

3
Silicon/TigerlakePkg/Library/IgdOpRegionLib/IgdOpRegionTgl.h → Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegion.h
View File

@ -4,14 +4,13 @@
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IGD_OPREGION_H_
#define _IGD_OPREGION_H_
/**
OpRegion structures:
Sub-structures define the different parts of the OpRegion followed by the

26
Silicon/TigerlakePkg/Library/IgdOpRegionLib/IgdOpRegionLib.c → Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.c
View File

@ -6,12 +6,11 @@
Acronyms:
IGD: Internal Graphics Device
NVS: ACPI Non Volatile Storage
OpRegion: ACPI Operational Region
VBT: Video BIOS Table (OEM customizable data)
IPU: Image Processing Unit
Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -27,9 +26,8 @@
#include <Library/MemoryAllocationLib.h>
#include <Library/BootloaderCommonLib.h>
#include "IgdOpRegionTgl.h"
#include "IgdOpRegion.h"
#include <IgdOpRegionDefines.h>
#include <GlobalNvsAreaDef.h>
#include "GopConfigLib.h"
//
@ -176,18 +174,20 @@ UpdateVbt (
EFI_STATUS
EFIAPI
IgdOpRegionInit (
IN GOP_VBT_UPDATE_CALLBACK GopVbtUpdateCallback
IN IGD_OP_PLATFORM_INFO *IgdPlatformInfo
)
{
GLOBAL_NVS_AREA *Gnvs;
UINT16 Data16;
UINT16 ExtendedVbtSize;
EFI_STATUS Status;
VBIOS_VBT_STRUCTURE *VbtFileBuffer;
GOP_VBT_UPDATE_CALLBACK VbtCallback;
UINT8 TurboIMON;
Status = EFI_ABORTED;
VbtFileBuffer = NULL;
ExtendedVbtSize = 0;
VbtCallback = NULL;
GetVbt (&VbtFileBuffer);
if (VbtFileBuffer == NULL) {
@ -205,11 +205,8 @@ IgdOpRegionInit (
}
SetMem(mIgdOpRegion.OpRegion, sizeof(IGD_OPREGION_STRUCTURE) + ExtendedVbtSize, 0);
//
// Update OpRegion address to Gnvs
//
Gnvs = (GLOBAL_NVS_AREA *)(UINTN)PcdGet32(PcdAcpiGnvsAddress);
Gnvs->SaNvs.IgdOpRegionAddress = (UINT32)(UINTN)(mIgdOpRegion.OpRegion);
Status = PcdSet32S (PcdIgdOpRegionAddress, (UINT32)(UINTN)(mIgdOpRegion.OpRegion));
//
// Initialize OpRegion Header
@ -254,7 +251,8 @@ IgdOpRegionInit (
//
// Reporting to driver for VR IMON Calibration. Bits [5-1] values supported 14A to 31A.
//
mIgdOpRegion.OpRegion->MBox3.PCFT = (Gnvs->SaNvs.GfxTurboIMON << 1) & 0x003E;
TurboIMON = (IgdPlatformInfo != NULL) ? IgdPlatformInfo->TurboIMON : 0x1F;
mIgdOpRegion.OpRegion->MBox3.PCFT = (TurboIMON << 1) & 0x003E;
///
/// Set Initial current Brightness
@ -289,7 +287,11 @@ IgdOpRegionInit (
CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VbtFileBuffer, VbtFileBuffer->HeaderVbtSize);
}
Status = UpdateVbt (ExtendedVbtSize > 0, GopVbtUpdateCallback);
VbtCallback = NULL;
if (IgdPlatformInfo != NULL) {
VbtCallback = IgdPlatformInfo->callback;
}
Status = UpdateVbt (ExtendedVbtSize > 0, VbtCallback);
if (EFI_ERROR (Status)) {
return Status;

8
Silicon/ElkhartlakePkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf → Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf
View File

@ -1,6 +1,6 @@
#/*++
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
@ -27,13 +27,15 @@
#
[Sources]
IgdOpRegion.h
GopConfigLib.h
IgdOpRegionLib.c
[Packages]
MdePkg/MdePkg.dec
BootloaderCorePkg/BootloaderCorePkg.dec
BootloaderCommonPkg/BootloaderCommonPkg.dec
Silicon/ElkhartlakePkg/ElkhartlakePkg.dec
Silicon/CommonSocPkg/CommonSocPkg.dec
[LibraryClasses]
BaseLib
@ -44,5 +46,5 @@
MemoryAllocationLib
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdAcpiGnvsAddress
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress
gPlatformModuleTokenSpaceGuid.PcdIgdOpRegionAddress

36
Silicon/ElkhartlakePkg/Include/Library/IgdOpRegionLib.h
View File

@ -1,36 +0,0 @@
/** @file
This is part of the implementation of an Intel Graphics drivers OpRegion /
Software SCI interface between system Bootloader, ASL code, and Graphics drivers.
The code in this file will load the driver and initialize the interface
Supporting Specification: OpRegion / Software SCI SPEC 0.70
Acronyms:
IGD: Internal Graphics Device
NVS: ACPI Non Volatile Storage
OpRegion: ACPI Operational Region
VBT: Video BIOS Table (OEM customizable data)
IPU: Image Processing Unit
Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _IGD_OP_REGION_LIB_H_
#define _IGD_OP_REGION_LIB_H_
/**
Graphics OpRegion / Software SCI driver installation function.
@param Void
@retval EFI_SUCCESS The driver installed without error.
@retval EFI_ABORTED The driver encountered an error and could not complete
installation of the ACPI tables.
**/
EFI_STATUS
IgdOpRegionInit (
void
);
#endif

221
Silicon/ElkhartlakePkg/Library/IgdOpRegionLib/IgdOpRegionLib.c
View File

@ -1,221 +0,0 @@
/** @file
This is part of the implementation of an Intel Graphics drivers OpRegion /
Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/IgdOpRegionLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/MemoryAllocationLib.h>
#include <IgdOpRegion.h>
#include <IgdOpRegionDefines.h>
#include <GlobalNvsAreaDef.h>
//
// Global variables
//
IGD_OPREGION_PROTOCOL mIgdOpRegion;
/**
Get VBT data.
@param[out] VbtFileBuffer Pointer to VBT data buffer.
@retval EFI_SUCCESS VBT data was returned.
@exception EFI_UNSUPPORTED Invalid signature in VBT data.
**/
EFI_STATUS
GetVbt (
OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer
)
{
EFI_PHYSICAL_ADDRESS VbtAddress = 0;
// Get the vbt address
VbtAddress = PcdGet32(PcdGraphicsVbtAddress);
DEBUG ((DEBUG_INFO, "VbtAddress =0x%x \n", VbtAddress));
// Check VBT signature
*VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;
if (*VbtFileBuffer != NULL) {
if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) != VBT_SIGNATURE) {
if (*VbtFileBuffer != NULL) {
*VbtFileBuffer = NULL;
}
return EFI_UNSUPPORTED;
}
// Check VBT size.
if ((*VbtFileBuffer)->HeaderVbtSize > 6*SIZE_1KB) {
(*VbtFileBuffer)->HeaderVbtSize = (UINT16) 6*SIZE_1KB;
}
}
return EFI_SUCCESS;
}
/**
Update VBT data in Igd Op Region.
@retval EFI_SUCCESS VBT data was returned.
@exception EFI_ABORTED Intel VBT not found.
**/
EFI_STATUS
UpdateVbt(
VOID
)
{
VBIOS_VBT_STRUCTURE *VbtFileBuffer = NULL;
GetVbt (&VbtFileBuffer);
if (VbtFileBuffer != NULL) {
DEBUG ((DEBUG_INFO, "VBT data found\n"));
DEBUG ((DEBUG_INFO, "VbtFileBuffer->HeaderVbtSize = 0x%x \n", VbtFileBuffer->HeaderVbtSize));
// Initialize Video BIOS version with its build number.
mIgdOpRegion.OpRegion->Header.Vver[0] = VbtFileBuffer->CoreBlockBiosBuild[0];
mIgdOpRegion.OpRegion->Header.Vver[1] = VbtFileBuffer->CoreBlockBiosBuild[1];
mIgdOpRegion.OpRegion->Header.Vver[2] = VbtFileBuffer->CoreBlockBiosBuild[2];
mIgdOpRegion.OpRegion->Header.Vver[3] = VbtFileBuffer->CoreBlockBiosBuild[3];
CopyMem (mIgdOpRegion.OpRegion->Vbt.Gvd1, VbtFileBuffer, VbtFileBuffer->HeaderVbtSize);
return EFI_SUCCESS;
} else {
DEBUG ((DEBUG_INFO, "Intel VBT not found\n"));
return EFI_ABORTED;
}
}
/**
Graphics OpRegion / Software SCI driver installation function.
@param[in] void - None
@retval EFI_SUCCESS - The driver installed without error.
@retval EFI_OUT_OF_RESOURCES - Could no allocate space for the IGD Op Region
@retval EFI_ABORTED - The driver encountered an error and could not complete
installation of the ACPI tables.
**/
EFI_STATUS
IgdOpRegionInit (
VOID
)
{
GLOBAL_NVS_AREA *Gnvs;
UINT16 Data16;
EFI_STATUS Status = EFI_ABORTED;
mIgdOpRegion.OpRegion = (IGD_OPREGION_STRUC *) AllocatePool (sizeof(IGD_OPREGION_STRUC));
if (mIgdOpRegion.OpRegion == NULL) {
return EFI_OUT_OF_RESOURCES;
}
SetMem(mIgdOpRegion.OpRegion, sizeof(IGD_OPREGION_STRUC), 0);
//
// Update OpRegion address to Gnvs
//
Gnvs = (GLOBAL_NVS_AREA *)(UINTN)PcdGet32(PcdAcpiGnvsAddress);
Gnvs->SaNvs.IgdOpRegionAddress = (UINT32)(UINTN)(mIgdOpRegion.OpRegion);
//
// Initialize OpRegion Header
//
CopyMem (mIgdOpRegion.OpRegion->Header.Sign, HEADER_SIGNATURE, sizeof(HEADER_SIGNATURE));
//
// Set OpRegion Size in KBs
//
mIgdOpRegion.OpRegion->Header.Size = HEADER_SIZE/1024;
mIgdOpRegion.OpRegion->Header.Over = (UINT32) (LShiftU64 (HEADER_OPREGION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));
//
// All Mailboxes are supported.
//
mIgdOpRegion.OpRegion->Header.MBox = HEADER_MBOX_SUPPORT;
//
// Initialize OpRegion Mailbox 1 (Public ACPI Methods).
//
// Note - The initial setting of mailbox 1 fields is implementation specific.
// Adjust them as needed many even coming from user setting in setup.
//
//
// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).
//
// Note - The initial setting of mailbox 3 fields is implementation specific.
// Adjust them as needed many even coming from user setting in setup.
//
//
// Do not initialize TCHE. This field is written by the graphics driver only.
//
//
// The ALSI field is generally initialized by ASL code by reading the embedded controller.
//
mIgdOpRegion.OpRegion->Header.PCon = 0x3;
mIgdOpRegion.OpRegion->MBox3.Bclp = BACKLIGHT_BRIGHTNESS;
mIgdOpRegion.OpRegion->MBox3.Pfit = (FIELD_VALID_BIT | PFIT_STRETCH);
//
// Reporting to driver for VR IMON Calibration. Bits [5-1] values supported 14A to 31A.
//
mIgdOpRegion.OpRegion->MBox3.Pcft = (Gnvs->SaNvs.GfxTurboIMON << 1) & 0x003E;
///
/// Set Initial current Brightness
///
mIgdOpRegion.OpRegion->MBox3.Cblv = (INIT_BRIGHT_LEVEL | FIELD_VALID_BIT);
// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table
// Possible 20 entries (example used 11), each 16 bits as follows:
// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
mIgdOpRegion.OpRegion->MBox3.Bclm[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///< 0%
mIgdOpRegion.OpRegion->MBox3.Bclm[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10%
mIgdOpRegion.OpRegion->MBox3.Bclm[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///< 20%
mIgdOpRegion.OpRegion->MBox3.Bclm[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30%
mIgdOpRegion.OpRegion->MBox3.Bclm[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///< 40%
mIgdOpRegion.OpRegion->MBox3.Bclm[5] = (0x327F + WORD_FIELD_VALID_BIT); ///< 50%
mIgdOpRegion.OpRegion->MBox3.Bclm[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60%
mIgdOpRegion.OpRegion->MBox3.Bclm[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70%
mIgdOpRegion.OpRegion->MBox3.Bclm[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///< 80%
mIgdOpRegion.OpRegion->MBox3.Bclm[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90%
mIgdOpRegion.OpRegion->MBox3.Bclm[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///< 100%
mIgdOpRegion.OpRegion->MBox3.Iuer = 0x00;
Status = UpdateVbt();
if (EFI_ERROR (Status)) {
return Status;
}
// Initialize hardware state:
// Set ASLS Register to the OpRegion physical memory address.
// Set SWSCI register bit 15 to a "1" to activate SCI interrupts.
PciWrite32(PCI_LIB_ADDRESS(IGD_BUS, IGD_DEV, IGD_FUN_0, IGD_ASLS_OFFSET), (UINT32)(UINTN)(mIgdOpRegion.OpRegion));
Data16 = PciRead16(PCI_LIB_ADDRESS(IGD_BUS, IGD_DEV, IGD_FUN_0, IGD_SWSCI_OFFSET));
Data16 &= ~BIT0;
Data16 |= BIT15;
PciWrite16(PCI_LIB_ADDRESS(IGD_BUS, IGD_DEV, IGD_FUN_0, IGD_SWSCI_OFFSET), Data16);
DEBUG ((DEBUG_INFO, "IgdOpRegion ended\n"));
return Status;
}

51
Silicon/TigerlakePkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf
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@ -1,51 +0,0 @@
#/*++
#
# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
# Module Name:
#
# IgdOpRegionLib.inf
#
# Abstract:
#
# Component description file for Igd Operation Region Library
#
#--*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IgdOpRegionLib
FILE_GUID = 98796601-6f1f-492e-8f53-546eebed43bc
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = IgdOpRegionLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM
#
[Sources]
IgdOpRegionTgl.h
GopConfigLib.h
IgdOpRegionLib.c
[Packages]
MdePkg/MdePkg.dec
BootloaderCorePkg/BootloaderCorePkg.dec
BootloaderCommonPkg/BootloaderCommonPkg.dec
Silicon/TigerlakePchPkg/TigerlakePchPkg.dec
Silicon/TigerlakePkg/TigerlakePkg.dec
[LibraryClasses]
BaseLib
IoLib
PcdLib
DebugLib
HobLib
MemoryAllocationLib
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdAcpiGnvsAddress
gPlatformModuleTokenSpaceGuid.PcdGraphicsVbtAddress