[TGL] Update ConfigTdpLevel

Set UPD ConfigTdpLevel in FSPM instead FSPS
Remove unused CFG data

Signed-off-by: Guo Dong <guo.dong@intel.com>

Platform/TigerlakeBoardPkg/CfgData/CfgData_Int_Tglu_Ddr4.dlt

@@ -10,7 +10,6 @@
 
 PLATFORMID_CFG_DATA.PlatformId           | 0x0001
 PLAT_NAME_CFG_DATA.PlatformName          | 'TGLU_DDR'
-#GEN_CFG_DATA.PayloadId                   | 'UEFI'
 
 MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch1     | { 0, 1}
 MEMORY_CFG_DATA.DqsMapCpu2DramMc0Ch3     | { 0, 1}

Platform/TigerlakeBoardPkg/CfgData/CfgData_Memory.yaml

@@ -639,7 +639,7 @@
       help         : >
                      Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
       length       : 0x01
-      value        : 0x00
+      value        : 0x0
   - PlatformDebugConsent :
       name         : Platform Debug Consent
       type         : Combo
@@ -647,7 +647,7 @@
       help         : >
                      To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options.\Manual- Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.\nNote- DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
       length       : 0x01
-      value        : 0x00
+      value        : 0x0
   - DciEn        :
       name         : DCI Enable
       type         : Combo
@@ -655,7 +655,7 @@
       help         : >
                      Determine if to enable DCI debug from host
       length       : 0x01
-      value        : 0x00
+      value        : 0x0
   - !expand { MEM_TMPL : [ Training ] }
   - RMT          :
       name         : Rank Margin Tool
@@ -705,27 +705,6 @@
                      Enables/Disable Early Command Training
       length       : 0x01
       value        : 0x01
-  - RaplLim1WindX :
-      name         : RAPL PL 1 WindowX
-      type         : EditNum, HEX, (0x01, 0x03)
-      help         : >
-                     Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-      length       : 0x01
-      value        : 0x0
-  - RaplLim1WindY :
-      name         : RAPL PL 1 WindowY
-      type         : EditNum, HEX, (0x01, 0x1F)
-      help         : >
-                     Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-      length       : 0x01
-      value        : 0x0
-  - RaplLim1Pwr  :
-      name         : RAPL PL 1 Power
-      type         : EditNum, HEX, (0x0, 0x3FFF)
-      help         : >
-                     range[0;2^14-1]= [2047.875;0]in W, (224= Def)
-      length       : 0x02
-      value        : 0x0
   - UsbTcPortEnPreMem :
       name         : TCSS USB Port Enable
       type         : EditNum, HEX, (0x0,0x003F)
@@ -741,7 +720,14 @@
                      Total Memory Encryption enabling
       length       : 0x01
       value        : 0x00
+  - ConfigTdpLevel :
+      name         : Configuration for boot TDP selection
+      type         : EditNum, HEX, (0x00, 0xFF)
+      help         : >
+                     Configuration for boot TDP selection; <b>0- TDP Nominal</b>; 1- TDP Down; 2- TDP Up;0xFF - Deactivate
+      length       : 0x01
+      value        : 0x00
   - Dummy        :
-      length       : 0x02
+      length       : 0x01
       value        : 0x0
 

Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml

@@ -244,14 +244,7 @@
                      Enable/disable Timed GPIO1    0- Disable; 1- Enable.
       length       : 0x01
       value        : 0x0
-  - ConfigTdpLevel :
-      name         : Configuration for boot TDP selection
-      type         : EditNum, HEX, (0x00, 0xFF)
-      help         : >
-                     Configuration for boot TDP selection; <b>0- TDP Nominal</b>; 1- TDP Down; 2- TDP Up;0xFF - Deactivate
-      length       : 0x01
-      value        : 0x02
   - Dummy        :
-      length       : 0x1
+      length       : 0x2
       value        : 0x0
 

Platform/TigerlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c

@@ -334,9 +334,6 @@ UpdateFspConfig (
   Fspmcfg->RMC                  = MemCfgData->RMC;
   Fspmcfg->MEMTST               = MemCfgData->MEMTST;
   Fspmcfg->ECT                  = MemCfgData->ECT;
-//    Fspmcfg->RaplLim1WindX        = MemCfgData->RaplLim1WindX;
-//    Fspmcfg->RaplLim1WindY        = MemCfgData->RaplLim1WindY;
-//    Fspmcfg->RaplLim1Pwr          = MemCfgData->RaplLim1Pwr;
 
   CopyMem (Fspmcfg->DmiGen3RootPortPreset, MemCfgData->DmiGen3RootPortPreset, sizeof(MemCfgData->DmiGen3RootPortPreset));
   CopyMem (Fspmcfg->DmiGen3EndPointPreset, MemCfgData->DmiGen3EndPointPreset, sizeof(MemCfgData->DmiGen3EndPointPreset));
@@ -479,6 +476,8 @@ UpdateFspConfig (
   Fspmcfg->PlatformDebugConsent = MemCfgData->PlatformDebugConsent;
   Fspmcfg->DciEn                = MemCfgData->DciEn;
 
+  Fspmcfg->ConfigTdpLevel       = MemCfgData->ConfigTdpLevel;
+
   // ES2 A1 silicon need set this to 1
   Fspmcfg->McParity = MemCfgData->McParity;
 

Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c

@@ -1572,7 +1572,6 @@ UpdateFspConfig (
   FspsConfig->ITbtPcieRootPortEn[3] = 0x1;
 
   if (SiCfgData != NULL) {
-    FspsConfig->ConfigTdpLevel = SiCfgData->ConfigTdpLevel;
     FspsConfig->EnableTimedGpio0 = SiCfgData->EnableTimedGpio0;
     FspsConfig->EnableTimedGpio1 = SiCfgData->EnableTimedGpio1;
     FspsConfig->XdciEnable       = SiCfgData->XdciEnable;