[EHL] Set SPI flash EISS and LE (#983)

Set SPI flash EISS and LE in EHL.

Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
This commit is contained in:
jinjhuli 2021-01-26 09:23:04 +08:00 committed by GitHub
parent c9be70efd2
commit 1faaabcd54
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 24 additions and 1 deletions

View File

@ -75,6 +75,7 @@
#include <TccConfigSubRegion.h>
#include <Library/MeExtMeasurementLib.h>
#include <Library/GpioLib.h>
#include <Register/RegsSpi.h>
UINT8 mTccRtd3Support;
@ -459,7 +460,22 @@ BuildOsConfigDataHob (
return EFI_SUCCESS;
}
/**
Set SPI flash EISS and LE
**/
VOID
ProgramSecuritySetting (
VOID
)
{
UINTN SpiBaseAddress;
SpiBaseAddress = GetDeviceAddr (OsBootDeviceSpi, 0);
SpiBaseAddress = TO_MM_PCI_ADDRESS (SpiBaseAddress);
// Set the BIOS Lock Enable and EISS bits
MmioOr8 (SpiBaseAddress + R_SPI_BCR, (UINT8) (B_SPI_BCR_BLE | B_SPI_BCR_EISS));
}
/**
Add a Smbios type string into a buffer
@ -789,6 +805,14 @@ BoardInit (
AppendS3Info ((VOID *)&mS3SaveReg);
}
}
if ((GetBootMode() != BOOT_ON_FLASH_UPDATE) && (GetPayloadId() != 0)) {
ProgramSecuritySetting ();
}
break;
case ReadyToBoot:
if ((GetBootMode() != BOOT_ON_FLASH_UPDATE) && (GetPayloadId() == 0)) {
ProgramSecuritySetting ();
}
break;
case EndOfFirmware:
break;

View File

@ -42,7 +42,6 @@
#define R_SPI_CFG_BAR0 0x10
// Flash Descriptpr Master section
#define B_FLASH_FMBA 0x0080 ///< Flash Master Base Address
#define R_FLMSTR1_BIOS 0x00 //Flash Master Host CPU/BIOS