IsMarkedBadDso and InvalidateBadDso would be required for all
the platforms that support TCC. And the implementation is also
common, so just move them to common TccLib.
Also updated the implementation to remove SPI flash erase for
InvalidateBadDso().
Signed-off-by: Guo Dong <guo.dong@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch invalidates the DSO region with a marker after
a DSO hang (caused by corrupted DSO) is detected (by WDT timeout).
With the marker, stage1b can know the DSO tuning should be skipped.
The bad DSO mark is defined as both Signature and Size in the
TCCT component header are zero.
With this patch, the previous defined WDT scratchpad bit,
WDT_FLAG_TCC_BAD_DSO, is removed.
TEST=Verified on TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
For bootguard event log fit header location is retrieved
from fit pointer. Added a condition to check the FIT header
range to fix KW error.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch solves an infinite reset loop issue caused
by bad DSO with the scenario:
After platform reset (due to WDT timeout), FSPm asks
for another reset, but before that, WDT_FLAG_TCC_DSO_IN_PROGRESS
is already cleaned. As a result, in the thrid reset, stage1B
will have no idea about the DSO is corrupted and it
continues boot with Tcc Tuning flow, which causes WDT
timeout reset again.
This patch introduces a WDT_FLAG_TCC_BAD_DSO flag in WDT
scrachpad (bit 18). The flag is a marker that is set when
a bad DSO is detected. The new booting flow for "bad DSO" case
if Tcc_Tuning enabled will be:
1st boot: (after fwupdate)
- TCC_DSO and WDT set by stage1b and stage2
- FSP hangs and trigger WDT reset
2nd boot:
- Stage1b detects "bad DSO" because of WDT and
TCC_DSO_IN_PROGRESS. For this case:
Clear TCC_DSO_IN_PROGRESS and WDT.
Set TCC_BAD_DSO.
Then it continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
- FSPm asks for a reset
3rd boot:
- Stage1b detects "bad DSO" because of TCC_BAD_DSO
It continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
The patch does not remove the 200-sec abnormal boot-up symptom
because the symptom is noticeable to user. So user can be aware
of something wrong (bad DSO).
The "bad DSO" flag will be clear before fwupdate, so a fwupdate
with a correct DSO can solve the 200 sec abnormal boot up time.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added additional files to be excluded from patch check.
For example, txt, ini, app, common, template, rule, Makefile,
GNUmakefile, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PatchChecker.py still complains lots of files with
trailing whitespace and tabs. This patch addressed these
error reporting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
Current SBL uses DLT file to override the GPIO group id in the
GPIO CFGDATA table because the group ID used in CFGDATA needs to
match the group ID used by GPIO library. This patch decoupled the
GPIO group id with the GPIO library. Instead, a translation was
added to convert the group ID to the value required by the GPIO
library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In certain condition, it is required to use fixed display mode. This
path added a new API SetVbtFixedMode() in BoardSupportLib to provide
such function. It can be used to request a fixed resolution at runtime
to run an application, such as setup screen.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current GPIO programming code in CommonSocPkg will override the
CFGDATA database. It tried to zero out the GPIO group ID and pad
ID from the GPIO CFGDATA entry. But it should only be applied to
the copied new entry, not the original entry in CFGDATA database.
This patch fixed this isue.
It fixed#1382.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to report memory size info in SMBIOS table, it is required
to know the full system memory. However, all info can only be passed
through FSP HOB, and it cannot easily identify the top of low/high
memory. The patch added core API GetMemoryInfo/SetMemoryInfo so that
platform can provide required memory info for core. By default, it
uses FSP hobs to guess these info. But platform can update it with
more accurate info during PostMemoryInit phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are too much ERROR level debug message in GPIO library. Since
ERROR level debug message will be stored in final release binary,
it increases the image size. This patch changed the GPIO DEBUG
level to VERBOSE by default to reduce binary size. When debug is
needed, we can change the debug level in the header file to allow
more detailed info.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
On TGL warm reset flow, current MRC will always do full MRC training.
It is because of wrong PMC rigster was used in platform code to set
and clear the MRC scratch pad bit.
This fixed#1346.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL build will show lots of FSP files as untracked files.
This patch re-orgnized the rules for .gitignore file so that it
has better control at different folder level. With these new rules
no untracked files will be shown for the FSP and VBT files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch clears RTC alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
In addition to clearing RTC SMI#, this patch also clears other
SMI# as UEFI BIOS does.
Test method: rtcwake -m -s 15
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- UP3 IoT FSP MR3
- change the FSP headers from FspBin folder to Include folder
- update TGL platform version to 1.3
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
On QEMU or Smimics, it might need to do native GFX initialization
if the GFX is not initialized by FSP. This patch added the native
GFX support for BOCHS graphics controller.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On Simics or QEMU, BOCHS graphics is used. This patch provides
library to initialize BOCHS graphics. It is useful when GFX
initiailzation is not provided by FSP. In this case, the native
code can be used to initialize graphics.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PciSegmentLib implementation from EDK2 MdePkg.
This library can be used by silicon libraries to access PCI
device with multiple segments. As part of this change, the
duplicated files were removed for CML and CMLV.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added payload selection GPIO configuration
hardcoded GPIO pin for payload selection.
It also fixed#1196.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Co-authored-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- enable s0ix by default for TGL-U
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This patch fixes a hang issue during fw update caused by
mismatching bios rom size. For a fw update, the TopSwap
size, Redundant Region size, and total BIOS region must be
identical.
This patch also adds check on rom size during fw update.
The check only works for a running SBL built with this patch.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
There is a discrepancy between how Linux reads GPIO
and how bootloader is presenting it. This causes Linux
distros to crash, even in the installer,unless a kernel
module parameter has been passed:
'module_blacklist=pinctrl_elkhartlake'
The customer, Red Hat, is using RHEL 8 4.18.0-315.
There appears to be a discrepancy between how Linux reads GPIO and how
the Intel BIOS is presenting it.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch clears RTC Alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
This patch also refactors RegRead/RegWrite in RestoreS3RegInfo
to avoid the misalingment of function pointers and coding
convention.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Add latest Intel® Time Coordinated Computing support for EHL.
Here are the changes:
- Update the TCC subregion layout
- Use the common TCC config data
- Use the common TCC library for RTCT table
- Support TCC DSO cfg, Cache cfg and CRL binaries loading
- Rename TCC variable to follow TCC V2 naming
- Increase the stage 2 size from 0x89000 to 0x91000 to accommodate
the new changes
- Add latest FspmUpd and FspsUpd header files for TCC v2 support
(will be removed once FSP github updated the latest EHL FSP package)
- Change default boot options for RTCM support
TCC mode is turned off by default.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
MR2 FSP is available so update SBL to use MR2 FSP.
and also use new Microcode required by new FSP
Update platform code on FSP UPDs, especially enable TCC feature.
Update TGL platform version to 1.2 since MR2 released.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Remove TGL-H GPIO definition and program.
Use R_ACPI_IO_SMI_STS instead of "R_ACPI_IO_SMI_EN + 4"
Set PCIE region len to 0x10000000 instead of 0x20000000
Remove data dumping for PSD
Fix other typo
Signed-off-by: Guo Dong <guo.dong@intel.com>
Guo Dong