For Azure and toolchain check we
can update to using IASL version
20190509 since some of the newer
SBL platforms require a newer
IASL version.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
BAD DSO mark is simplified to only use Signature=0
when moving DSO update/check to TccLib.
Related check in fwupdate has to be updated too.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
IsMarkedBadDso and InvalidateBadDso would be required for all
the platforms that support TCC. And the implementation is also
common, so just move them to common TccLib.
Also updated the implementation to remove SPI flash erase for
InvalidateBadDso().
Signed-off-by: Guo Dong <guo.dong@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch invalidates the DSO region with a marker after
a DSO hang (caused by corrupted DSO) is detected (by WDT timeout).
With the marker, stage1b can know the DSO tuning should be skipped.
The bad DSO mark is defined as both Signature and Size in the
TCCT component header are zero.
With this patch, the previous defined WDT scratchpad bit,
WDT_FLAG_TCC_BAD_DSO, is removed.
TEST=Verified on TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
For bootguard event log fit header location is retrieved
from fit pointer. Added a condition to check the FIT header
range to fix KW error.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Since openssl 3.0.0, in commit 10203a34725e ("Support writing RSA
keys using the traditional format again"), the default format of
private key has been changed to PKCS#8.
Signed-off-by: Yongxin Liu <yongxin.liu@windriver.com>
Currently StitchLoader.py is under platform package, and
the common tool BtgSign.py should not depend on that tool.
And BtgSign.py indeed doesn't depend on it, so just update
it to make it could work without StitchLoader.py.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Rearrange SBL Global Data Structure for POSC
issue workaround. This is due to the POSC accessing
SBL Global Data and it get corrupted when SBL rearrange
or restructure the data structure.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
On CFL and CML, the board hook PostMemoryInit was called before
FspMemoryInit API. This should be called afterwards instead.
This patch fixed this issue. It is because of missing "break"
statement. It fixed#1435.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When BOARD_PKG_NAME_OVERRIDE is configured, the tool will firstly
search from BOARD_PKG_NAME_OVERRIDE, then search BOARD_PKG_NAME
for dlt and vbt files. It also uses BOARD_PKG_NAME_OVERRIDE for the
VerInfo file.
Signed-off-by: Guo Dong <guo.dong@intel.com>
EDK2 stable tag 202111 changed some field name in SMBIOS structure.
This patch matched the changes to fix the build issue for SBL. It
also added new library class in DSC.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch solves an infinite reset loop issue caused
by bad DSO with the scenario:
After platform reset (due to WDT timeout), FSPm asks
for another reset, but before that, WDT_FLAG_TCC_DSO_IN_PROGRESS
is already cleaned. As a result, in the thrid reset, stage1B
will have no idea about the DSO is corrupted and it
continues boot with Tcc Tuning flow, which causes WDT
timeout reset again.
This patch introduces a WDT_FLAG_TCC_BAD_DSO flag in WDT
scrachpad (bit 18). The flag is a marker that is set when
a bad DSO is detected. The new booting flow for "bad DSO" case
if Tcc_Tuning enabled will be:
1st boot: (after fwupdate)
- TCC_DSO and WDT set by stage1b and stage2
- FSP hangs and trigger WDT reset
2nd boot:
- Stage1b detects "bad DSO" because of WDT and
TCC_DSO_IN_PROGRESS. For this case:
Clear TCC_DSO_IN_PROGRESS and WDT.
Set TCC_BAD_DSO.
Then it continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
- FSPm asks for a reset
3rd boot:
- Stage1b detects "bad DSO" because of TCC_BAD_DSO
It continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
The patch does not remove the 200-sec abnormal boot-up symptom
because the symptom is noticeable to user. So user can be aware
of something wrong (bad DSO).
The "bad DSO" flag will be clear before fwupdate, so a fwupdate
with a correct DSO can solve the 200 sec abnormal boot up time.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Config 1/3 RVP boards can't share same IFWI image
and it is required to adjust the FIT parameters.
Add -o cfg3 to support this.
Signed-off-by: Randy Lin <randy.lin@intel.com>
The timestamp value is saved in edi:esi at reset vector in X64, but
PreparePagingTable is using esi and makes 1st timestamp value invalid.
This saves/restores edi:esi before/after PreparePagingTable to keep
proper timestamp value at reset vector.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch fixed the issue that "cfgdata_dir" argument is not
used properly by the CfgDataStitch script. The "cfgdata_dir"
will contain the CfgDataDef.yaml file and optional DLT files
if provided. Otherwise, the DLT files will be extracted from
the IFWI binary and stored in "cfgdata_dir".
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Adding the following bit of debug code to DetectUsedStackBottom() in
BootloaderCommonPkg/Library/BootloaderCommonLib/BootloaderCommonLib.c:
@@ -290,7 +290,10 @@ DetectUsedStackBottom (
{
UINT32 *StackBot;
+ DEBUG ((DEBUG_INFO, "StackTop is %x\n", StackTop));
StackBot = (UINT32 *) ((StackTop - StackSize) & ~ (sizeof (UINTN) - 1));
+ DEBUG ((DEBUG_INFO, "StackBot is %p %x\n", StackBot, *StackBot));
ASSERT (*StackBot == STACK_DEBUG_FILL_PATTERN);
while ((UINT32)(UINTN)StackBot < StackTop) {
shows this for the Stage1 stack on qemu X64, as expected:
StackTop is 2000
StackBot is 0 5AA55AA5
but it shows this on qemu Ia32, which appears to be incorrect:
StackTop is 2004
StackBot is 4 5AA55AA5
This Stage1 StackTop mismatch on Ia32 seems to be caused by the setup
code in BootloaderCorePkg/Stage1A/Ia32/SecEntry.nasm pushing only a single
32-bit word onto the stack for the 'Status' field of STAGE1A_ASM_PARAM,
while that field is actually a 64-bit field, which causes this line in
BootloaderCorePkg/Stage1A/Stage1A.c to compute a stack top address that
is off by 4 bytes:
StackTop = (UINT32)(UINTN)Params + sizeof (STAGE1A_ASM_PARAM);
This patch makes the Ia32 Stage1A setup code push an extra 32-bit
word onto the stack before calling SecStartup, which fixes the Stage1
StackTop computation.
While we are at it, let's push another dummy word onto the stack in
the Stage1A setup code to make the Stage1A stack be 16-byte aligned,
like what is already the case for X64, so that we follow Version 1.0
of the System V Intel386 ABI supplement, and satisfy any expectations
our compiler may have regarding stack alignment.
Also add a comment to both the Ia32 and X64 Stage1A setup code to
remind the reader that the structure we build on the stack before
calling SecStartup has to match the layout of STAGE1A_ASM_PARAM.
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
Much like the corresponding Stage1A patch, this patch aligns the
Ia32 Stage1B and Stage2 stacks to 16 bytes, like what is already the
case for X64, so that we follow Version 1.0 of the System V Intel386
ABI supplement, and satisfy any expectations our compiler may have
regarding stack alignment.
A nice side effect of this change is that it allows building an Ia32
Slimbootloader with -msse which can run on real hardware, which requires
16-byte stack alignment. Slimbootloader currently already enables SSE
in XCR0 early on in Stage1A, and it has SSE versions of various helper
functions written in assembly, in other words, it already makes use of
SSE, but allowing the compiler to emit SSE instructions requires 16-byte
stack alignment, because access to unaligned on-stack SSE variables
will throw #GP on real hardware. (QEMU doesn't seem to enforce the
requirement for natural alignment of SSE memory arguments.)
Suggested-by: Peter Edwards <peadar@arista.com>
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
When we die due to a fatal exception, we get a debug message that
looks like this:
Exception #6 from 0x0010:0x000728E9 !!!
This message by itself is not incredibly useful for figuring out
which code caused the exception.
This patch borrows an idea from the Linux kernel, and extends the
exception information with a dump of the opcode bytes around the
instruction pointer, which means that the exception debug message
will now look like this:
Exception #6 from 0x0010:0x000728E9 !!!
000728C9: 07 00 6A 40 E8 E0 E8 FF-FF 83 C4 0C 68 00 00 07 [...]
000728D9: 00 68 DA 3A 07 00 6A 40-E8 CC E8 FF FF 83 C4 10 [...]
000728E9: 0F 0B E8 8E F2 FF FF 8D-55 98 80 78 0E 01 8D 45 [...]
000728F9: 94 75 06 52 50 6A 01 EB-04 52 50 6A 00 68 53 47 [...]
Tested by inserting a UD2 instruction into Stage1A and verifying on
qemu ia32 and on qemu x64 that the right information is printed.
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
GPIO payload selection settings can be made
into a platform optional common config. This
will ensure that the options display the same
across all platforms which add support for
the GPIO payload selection feature. Each
platform will need to include the
CfgData_PayloadSelection.yaml and needs to
create their own CfgData_GpioPadGroups.yaml
to provide the list of GPIO pad groups to
select from.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch does the following updates to SmBiosInitLib:
1. Provide AddSmbiosType() to add a SmBios Type header.
2. Provide AddSmbiosString() to append strings to Type header.
3. Move Finalize() to after 'PrePayloadLoading' board init phase.
All Smbios related calls need to be done before this.
4. Modified TGL project to adjust to these changes.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Increase epayload size to 0x00162000 for compilation
error with latest debug version of uefi-payload
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
If the number of cores are more and the RTCM is
required to support HyperThreading, then it needs
more reserved size, preferably 511 pages instead of
current 255 pages.
So, add a FixedPcd and let each platform override
the default 255 pages value to whatever is required.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
When multiple USB devices are attached, current SBL will try to
boot the device with index specified by HwPart in the boot option.
However, it is hard to determine the USB device index order since
it depends on which port the device is connected to. Instead, for
USB devices, SBL can try to boot from each of them until the boot
image is loaded successfully or all USB devices have been tried out.
This patch added this support.
To enable this feature, it is required to set the USB boot option
HwPart to 0xFF.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added additional files to be excluded from patch check.
For example, txt, ini, app, common, template, rule, Makefile,
GNUmakefile, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added additional files to be excluded from patch check.
For example, txt, ini, app, common, template, rule, Makefile,
GNUmakefile, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PatchChecker.py still complains lots of files with
trailing whitespace and tabs. This patch addressed these
error reporting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
SBL might change MTRR to enable framebuffer cache. Current code
only handles BSP MTRR programming, and it is necessary to sync
up the MTRR programming for all APs as well. This patch added
a function to sync up MTRRs for all APs.
Please note, this MTRR sync up is a simplified version for SBL
case since SBL will only add new MTRRs for GFX framebuffer.
To do a full generic MTRRs sync up, it is required to flush cache,
reload TLB, etc. And it will come with some performance impacts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For EXT2 filesystem revision 0, there are some fixed fields in the
super block structure according to the documentation. The code should
always use those fixed values for safe regardless of the value inside
the image.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
James Gutbub