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[EHL] Rename LowPowerS0Idle to S0ix 

For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This commit is contained in:
Lean Sheng Tan 2021-08-11 02:14:12 +08:00 committed by Aiden Park
parent 5ae51f68fd
commit a7063eb30a
8 changed files with 70 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Platform/ElkhartlakeBoardPkg/CfgData/CfgData_Ext_IotgCrb.dlt
View File

@ -25,8 +25,9 @@ GPIO_CFG_DATA.GpioPinConfig1_GPP_D13.GPIOSkip_GPP_D13 | 0
# Enable to test TCC mode & tuning
# FEATURES_CFG_DATA.Features.Tcc | 0x1
FEATURES_CFG_DATA.Features.LowPowerIdle | 0x1
FEATURES_CFG_DATA.Features.NewGpioSchemeEnable | 0x1
# Enable S0ix by default. For EHL, only S0i2.0 is supported
FEATURES_CFG_DATA.Features.S0ix | 0x1
# Preserve ISI SPI Pins across ResetResume power-cycling
GPIO_CFG_DATA.GpioPinConfig1_GPP_U04.GPIOSkip_GPP_U04 | 0x0

6
Platform/ElkhartlakeBoardPkg/CfgData/CfgData_Features.yaml
View File

@ -41,12 +41,12 @@
help : >
To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. Enabling this BIOS option may alter the default value of other debug-related BIOS options.\Manual- Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.\nNote- DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
length : 3b
- LowPowerIdle :
name : Low Power Idle Enable
- S0ix :
name : S0ix (Low Power Idle) Enable
type : Combo
option : $EN_DIS
help : >
Enable/Disable Low Power Idle feature. 1:Low Power Idle Enabled, 0:Low Power Idle Disabled
Enable/Disable S0ix feature. 1:S0ix Enabled, 0:S0ix Disabled
length : 1b
- NewGpioSchemeEnable :
name : New GPIO Scheme Enable

49
Platform/ElkhartlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -207,6 +207,7 @@ TccModePreMemConfig (
FspmUpd->FspmConfig.RaplLim2Ena = PolicyConfig->MemoryRapl;
FspmUpd->FspmConfig.PowerDownMode = PolicyConfig->MemPowerDown;
FspmUpd->FspmConfig.DisPgCloseIdleTimeout = PolicyConfig->DisPgCloseIdle;
PLAT_FEAT.S0ixEnable = PolicyConfig->Sstates;
DEBUG ((DEBUG_INFO, "Dump TCC DSO BIOS settings:\n"));
DumpHex (2, 0, sizeof(BIOS_SETTINGS), PolicyConfig);
}
@ -222,6 +223,7 @@ TccModePreMemConfig (
DEBUG ((DEBUG_INFO, "SoftwareSramEnPreMem = %x\n", FspmUpd->FspmConfig.SoftwareSramEnPreMem ));
DEBUG ((DEBUG_INFO, "DsoTuningEnPreMem = %x\n", FspmUpd->FspmConfig.DsoTuningEnPreMem ));
DEBUG ((DEBUG_INFO, "TccErrorLogEnPreMem = %x\n", FspmUpd->FspmConfig.TccErrorLogEnPreMem ));
DEBUG ((DEBUG_INFO, "Tcc s0ix support = %x\n", S0IX_STATUS() ));
// Load Tcc Cache config from container
TccCacheBase = NULL;
@ -239,6 +241,36 @@ TccModePreMemConfig (
return Status;
}
/**
Update S0ix flag
**/
VOID
UpdateS0ixStatus (
VOID
)
{
FEATURES_CFG_DATA *FeaturesCfgData;
BOOLEAN PchSciSupported;
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
if (FeaturesCfgData == NULL) {
DEBUG ((DEBUG_INFO, "Failed to find Cfg Config Data! S0ix setting failed.\n"));
return;
}
PchSciSupported = PchIsSciSupported ();
// EHL S0ix condition depends on:
// - user turn on via config data
// - not FUSA sku
// - TCC config turns it on
if (PchSciSupported == 1 || FeaturesCfgData->Features.S0ix == 0 || S0IX_STATUS() == 0) {
PLAT_FEAT.S0ixEnable = 0;
} else {
PLAT_FEAT.S0ixEnable = 1;
}
DEBUG ((DEBUG_INFO, "S0ix Status = %x\n", S0IX_STATUS()));
}
/**
Update FSP-M UPD config data
@ -259,7 +291,6 @@ UpdateFspConfig (
SECURITY_CFG_DATA *SecCfgData;
UINT32 Index;
UINT8 DebugPort;
FEATURES_CFG_DATA *FeaturesCfgData;
BOOLEAN PchSciSupported;
TCC_CFG_DATA *TccCfgData;
@ -330,7 +361,6 @@ UpdateFspConfig (
}
CopyMem (&Fspmcfg->DmiGen3RxCtlePeaking, MemCfgData->DmiGen3RxCtlePeaking, sizeof(MemCfgData->DmiGen3RxCtlePeaking));
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
// SA:TCSS_PEI_PREMEM_CONFIG
Fspmcfg->UsbTcPortEnPreMem = MemCfgData->UsbTcPortEnPreMem;
Fspmcfg->PcieMultipleSegmentEnabled = MemCfgData->PcieMultipleSegmentEnabled;
@ -340,11 +370,6 @@ UpdateFspConfig (
Fspmcfg->TcssItbtPcie3En = MemCfgData->TcssItbtPcie3En;
Fspmcfg->TcssXhciEn = MemCfgData->TcssXhciEn;
Fspmcfg->TcssXdciEn = MemCfgData->TcssXdciEn;
if (FeaturesCfgData != NULL) {
if (FeaturesCfgData->Features.LowPowerIdle != 0 && PchSciSupported != 1){
Fspmcfg->TcssXdciEn = 0;
}
}
Fspmcfg->TcssDma0En = MemCfgData->TcssDma0En;
Fspmcfg->TcssDma1En = MemCfgData->TcssDma1En;
@ -717,9 +742,19 @@ UpdateFspConfig (
DEBUG ((DEBUG_INFO, "Failed to find GFX CFG!\n"));
}
// Enable s0ix by default
PLAT_FEAT.S0ixEnable = 1;
if (FeaturePcdGet (PcdTccEnabled)) {
TccModePreMemConfig (FspmUpd);
}
UpdateS0ixStatus ();
if (S0IX_STATUS() == 1) {
// configure FSP-M upd for s0ix
Fspmcfg->TcssXdciEn = 0;
}
}
/**

34
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -81,7 +81,6 @@
BOOLEAN mTccDsoTuning = FALSE;
UINT8 mTccRtd3Support = 0;
UINT8 mTccLowPowerS0Idle = 0;
//
// GPIO_PAD Fileds
@ -807,7 +806,7 @@ TccModePostMemConfig (
TCC_STREAM_CONFIGURATION *StreamConfig;
TCC_CFG_DATA *TccCfgData;
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag(CDATA_TCC_TAG);
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag (CDATA_TCC_TAG);
if ((TccCfgData == NULL) || ((TccCfgData->TccEnable == 0) && (TccCfgData->TccTuning == 0))) {
return EFI_NOT_FOUND;
}
@ -876,10 +875,10 @@ TccModePostMemConfig (
FspsUpd->FspsConfig.PcieRpAspm[Index] = PolicyConfig->PchPcieAspm;
FspsUpd->FspsConfig.PcieRpL1Substates[Index] = PolicyConfig->PchPcieRpL1;
}
mTccRtd3Support = PolicyConfig->Dstates;
mTccLowPowerS0Idle = PolicyConfig->Sstates;
mTccDsoTuning = TRUE;
if (mPchSciSupported != 0) {
mTccRtd3Support = PolicyConfig->Dstates;
}
}
}
@ -899,7 +898,6 @@ TccModePostMemConfig (
DEBUG ((DEBUG_INFO, "PcieRpAspm = %x\n", FspsUpd->FspsConfig.PcieRpAspm[0] ));
DEBUG ((DEBUG_INFO, "PcieRpL1Substates = %x\n", FspsUpd->FspsConfig.PcieRpL1Substates[0] ));
DEBUG ((DEBUG_INFO, "Rtd3Support = %x\n", mTccRtd3Support ));
DEBUG ((DEBUG_INFO, "LowPowerS0Idle = %x\n", mTccLowPowerS0Idle ));
// Load TCC cache config binary from container
TccCacheconfigBase = NULL;
@ -1098,10 +1096,8 @@ UpdateFspConfig (
FLASH_REGION_TYPE RegionType;
FSPS_UPD *FspsUpd;
FSP_S_CONFIG *Fspscfg;
SECURITY_CFG_DATA *SecCfgData;
SILICON_CFG_DATA *SiCfgData;
POWER_CFG_DATA *PowerCfgData;
FEATURES_CFG_DATA *FeaturesCfgData;
UINT8 SaDisplayConfigTable[17] = { 0 };
FspsUpd = (FSPS_UPD *)FspsUpdPtr;
@ -1110,15 +1106,6 @@ UpdateFspConfig (
if (SiCfgData == NULL) {
DEBUG ((DEBUG_INFO, "Failed to find Silicon CFG!\n"));
}
SecCfgData = (SECURITY_CFG_DATA *)FindConfigDataByTag (CDATA_SECURITY_TAG);
if (SecCfgData != NULL) {
DEBUG ((DEBUG_INFO, "Load Security Cfg Data\n"));
// Configure Sgx SPD Data (Removed due to fsp 2233)
//Fspscfg->SgxEpoch0 = SecCfgData->SgxEpoch0;
//Fspscfg->SgxEpoch1 = SecCfgData->SgxEpoch1;
} else {
DEBUG ((DEBUG_INFO, "Failed to find security CFG!\n"));
}
// eMMC, SdCard
Fspscfg->ScsEmmcEnabled = 1;
@ -1201,13 +1188,7 @@ UpdateFspConfig (
if (SiCfgData != NULL) {
// Xdci
Fspscfg->XdciEnable = SiCfgData->XdciEnable;
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
if (FeaturesCfgData != NULL) {
if (FeaturesCfgData->Features.LowPowerIdle != 0 && mPchSciSupported != 1){
Fspscfg->XdciEnable = 0;
}
}
Fspscfg->XdciEnable = SiCfgData->XdciEnable;
//CPU Config Data
Fspscfg->AesEnable = SiCfgData->AesEnable;
@ -1782,7 +1763,10 @@ UpdateFspConfig (
Fspscfg->EnableTcoTimer = TRUE;
DEBUG ((DEBUG_INFO, "Firmware update mode, unlock Bios setting\n"));
}
if (S0IX_STATUS() == 1) {
// configure s0ix related FSP-S config
Fspscfg->XdciEnable = 0;
}
}

19
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/UpdateAcpiGnvs.c
View File

@ -537,9 +537,7 @@ PlatformUpdateAcpiGnvs (
PchNvs = (PCH_NVS_AREA *) &GlobalNvs->PchNvs;
CpuNvs = (CPU_NVS_AREA *) &GlobalNvs->CpuNvs;
SaNvs = (SYSTEM_AGENT_NVS_AREA *) &GlobalNvs->SaNvs;
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
ZeroMem (GlobalNvs, sizeof (GLOBAL_NVS_AREA));
SiCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
//
// Update ASL PCIE port address according to root port device and function
@ -678,6 +676,7 @@ PlatformUpdateAcpiGnvs (
if (PseCanPciMmBase != 0xFFFF) {
PchNvs->PseCan1Enabled = 1;
}
SiCfgData = (SILICON_CFG_DATA *)FindConfigDataByTag (CDATA_SILICON_TAG);
if (SiCfgData != NULL) {
PchNvs->EnableTimedGpio0 = (UINT8)SiCfgData->EnableTimedGpio0;
PchNvs->EnableTimedGpio1 = (UINT8)SiCfgData->EnableTimedGpio1;
@ -704,7 +703,6 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->PlatformFlavor = 1;
PlatformNvs->Rtd3Support = 1;
PlatformNvs->Rtd3P0dl = 0x64;
PlatformNvs->Rtd3AudioDelay = 0xC8;
PlatformNvs->Rtd3SensorHub = 0x44;
@ -717,14 +715,10 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->ApicEnable = 1;
PlatformNvs->EcAvailable = 0;
PlatformNvs->LowPowerS0Idle = 0;
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag (CDATA_FEATURES_TAG);
if (FeaturesCfgData != NULL) {
if (FeaturesCfgData->Features.LowPowerIdle != 0 && PchSciSupported != 1){
PlatformNvs->LowPowerS0Idle = 1;
}
PlatformNvs->NewGpioSchemeEnable = (UINT8) FeaturesCfgData->Features.NewGpioSchemeEnable;
}
DEBUG((DEBUG_INFO, "PlatformNvs->LowPowerS0Idle = 0x%x\n ", PlatformNvs->LowPowerS0Idle));
DEBUG((DEBUG_INFO, "PlatformNvs->NewGpioSchemeEnable = 0x%x\n ", PlatformNvs->NewGpioSchemeEnable));
PlatformNvs->TenSecondPowerButtonEnable = 8;
@ -898,15 +892,12 @@ PlatformUpdateAcpiGnvs (
PlatformNvs->PpmFlags = CpuNvs->PpmFlags;
SocUpdateAcpiGnvs ((VOID *)GnvsIn);
if (PchSciSupported) {
PlatformNvs->Rtd3Support = 0;
PlatformNvs->LowPowerS0Idle = 0;
}
PlatformNvs->Rtd3Support = PchSciSupported? 0 : 1;
// If TCC is enabled, use the TCC policy from subregion
if (mTccDsoTuning) {
PlatformNvs->Rtd3Support = mTccRtd3Support;
PlatformNvs->LowPowerS0Idle = mTccLowPowerS0Idle;
}
PlatformNvs->LowPowerS0Idle = S0IX_STATUS();
DEBUG((DEBUG_INFO, "PlatformNvs->S0ix = 0x%x\n ", PlatformNvs->LowPowerS0Idle));
}

13
Platform/ElkhartlakeBoardPkg/Library/Stage2BoardInitLib/UpdateAcpiTable.c
View File

@ -29,6 +29,7 @@
#include <Lpit.h>
#include <Register/PmcRegs.h>
#include <Library/PchSciLib.h>
#include <PlatformData.h>
#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T')
@ -375,11 +376,9 @@ PlatformUpdateAcpiTable (
EFI_STATUS Status;
TCC_CFG_DATA *TccCfgData;
VOID *FspHobList;
FEATURES_CFG_DATA *FeaturesCfgData;
EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
GlobalNvs = (GLOBAL_NVS_AREA *)(UINTN) PcdGet32 (PcdAcpiGnvsAddress);
FeaturesCfgData = (FEATURES_CFG_DATA *) FindConfigDataByTag(CDATA_FEATURES_TAG);
Table = (EFI_ACPI_DESCRIPTION_HEADER *) Current;
Ptr = (UINT8 *)Table;
@ -438,7 +437,7 @@ PlatformUpdateAcpiTable (
DEBUG ((DEBUG_INFO, "Find RTCT table\n"));
if (FeaturePcdGet (PcdTccEnabled)) {
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag(CDATA_TCC_TAG);
TccCfgData = (TCC_CFG_DATA *) FindConfigDataByTag (CDATA_TCC_TAG);
if ((TccCfgData != NULL) && (TccCfgData->TccEnable != 0)) {
Status = UpdateAcpiRtctTable(Table);
DEBUG ( (DEBUG_INFO, "Updated ACPI RTCT Table : %r\n", Status) );
@ -459,11 +458,9 @@ PlatformUpdateAcpiTable (
// The Flags field within the FADT (offset 112)
// 1) will have a new Low Power S0 Idle Capable ACPI flag (bit offset 21).
//
if (FeaturesCfgData != NULL) {
if (FeaturesCfgData->Features.LowPowerIdle != 0 && PchIsSciSupported() != 1){
DEBUG ( (DEBUG_INFO, "Enabled Low Power S0 Idle Capable ACPI flag\n") );
FadtPointer->Flags = (EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE | FadtPointer->Flags);
}
if (S0IX_STATUS()) {
DEBUG ( (DEBUG_INFO, "Enabled S0ix ACPI flag\n") );
FadtPointer->Flags = (EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE | FadtPointer->Flags);
}
} else if (Table->Signature == EFI_ACPI_6_1_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE){
UINT8 LpitStateEntries = 0;

6
Silicon/ElkhartlakePkg/Include/PlatformData.h
View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2018 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -22,7 +22,8 @@ typedef struct {
typedef struct {
UINT32 VtdEnable : 1;
UINT32 DebugConsent : 3;
UINT32 Rsvd : 28;
UINT32 S0ixEnable : 1;
UINT32 Rsvd : 27;
} PLAT_FEATURES;
typedef struct {
@ -33,5 +34,6 @@ typedef struct {
#define PLAT_DATA ((PLATFORM_DATA *)GetPlatformDataPtr ())
#define PLAT_FEAT (PLAT_DATA->PlatformFeatures)
#define DEBUG_CONSENT_FEATURE_ENABLED() (UINT8) (PLAT_FEAT.DebugConsent)
#define S0IX_STATUS() (BOOLEAN) (PLAT_FEAT.S0ixEnable)
#endif /* __PLATFORM_DATA_H__ */

1
Silicon/ElkhartlakePkg/Include/TccConfigSubRegions.h
View File

@ -9,7 +9,6 @@
extern BOOLEAN mTccDsoTuning;
extern UINT8 mTccRtd3Support;
extern UINT8 mTccLowPowerS0Idle;
///
/// TCC BIOS Configuration