- Enable Tcc code path for N series.
- Disable WDT lock UPD since its causing the WDT to expire
even when valid DSO is provided.
- Code clean-up.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
When S0ix feature is enabled, some controllers are disabled
and ethernet/lan is one of them. Hence, disable by default so
that other controllers can be enabled by default.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Found PSDS ACPI table reporting incorrect value
and fixing by referring the BIOS method to retrieve
right value. Also Enable Platform Security Discovery.
Verify on CRB platform.
Signed-off-by: Randy Lin <randy.lin@intel.com>
The patch fixes GPIO group pin to pad issue, caused by GPPC_A0
starts from the bit offset 8 instead of 0 in all registers of
mPchHGpioGroupInfo[0].
The patch also updates the GPIO settings of GPP-A group for TGL-H RVP.
Verified: TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- Updated GPIO table to match BIOS PV ER3 release.
- Disable SCI for D13 and E00.
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
- Move DEBUG CODE END to later part of the GPIO function in
order to add GPIO prints when required.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixes the KW issue that is reported due to NULL
pointer deference. Moved up the code where CfgData checks for NULL.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixed BDF for UFS device, bus number and function
number are improperly ported and this patch fixed the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the hang seen during a reboot cmd on ADLS DDR4 board.
Setting the DmiMaxLinkSpeed to Auto mode.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
HsPhy feature is only applicable for ADLS and not for others.
Adding a condition to apply only for it.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch added support to get csme boot time performance
data and display it in perf command and also before booting
to linux.
Introduced a board config option BOOT_PERFORMANCE_MASK to control
PcdBootPerformanceMask, BIT 2 now enables printing CSME boot
performance data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Sync from EHL BIOS.
Error: ACPI BIOS Error (bug): AE_AML_BUFFER_LIMIT, Field [IOF2] at
bit offset/length 712/16 exceeds size of target Buffer (664 bits)
Signed-off-by: Randy Lin <randy.lin@intel.com>
Update FSP UPDs and VBT changes as part of the ADLP MR release.
TEST=Tested to boot to OS.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
*Adds code to support the updating
of ACM FW via capsule
*Adds code that disallows for the
roll back of ACM FW
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This patch can reduce the chance of setting SBL_SOURCE when the
SBL root directory is not named as "SblOpen" or when the scripts
are run from the path other than the SBL root directory. Also note
that os.path.abspath() returns the absolute path relative to the
current working directory instead of the real path of __file__.
So in StitchIfwi.py, sblopen_dir was incorrect since the working
directory had been changed before calling stitch().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
FSPT doesn't allow to enable full flash code cache.
Bootloader configures MTRR in non BTG cases to avoid
performance penalty.
This fixes the ADL boot from BP1 partition.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
PSE is enabled by default.
During SBL building, it will check the existance of PSE FW binary.
If it is missing in binaries folder, the PSEF won't be appended in
container list and casue StitchIFWI script fail if it try to update.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Also set the CpuTempSensorReadEnable = 1
It was renamed from PchCpuTempSensorEnable
and removed in commit 44faa431c9
Signed-off-by: Randy Lin <randy.lin@intel.com>
The default FSP UPD value for Lp5BankMode doesn't work
for all the platforms. It would help override it using
SBL configuration data if it is exposed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added changes required for ADLN FSP Sync and
also did the following
1) Added SA config for DDR5 CRB
2) Initialized VBT to enable 2 HDMI and a DP port
3) Moved FSPM config to delta file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This reverts commit 1caacefeb5.
The USB port that does not respond to USB bus enumeration is port 8 on
the newer UPX board. The old UPX board might have different behavior.
The original commit was valid on old UPX board only, and this patch
reverted it. Confirmed the USB error message disappeared on the new
UPX board after the reverting.
Signed-off-by: Maurice Ma <mauricemx.ma@gmail.com>
Only enabled IehMode when IBECC error injection is disabled
Iehmode will cause failure in IBECC error injection test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Match the FSP include path from Board Config to that of
FspBin inf file so it fixes the build issue.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
By default OsLoader payload shell is only available in debug build.
In some case customer also wants to have shell in release build.
So add a BootToShell configuration item to enable shell in release build.
By default BootToShell is set to 0. When it is set to 1 the shell behavior
would be same in release and debug build.
NOTE: user could add this line in platform dlt file to set BootToShell.
GEN_CFG_DATA.BootToShell |1
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch assigns Timed GPIO Cfg Data to the NVS variables
in order for the OS to load this driver.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
* Generate platform build name definition
Same code could be shared by different platforms. At same time,
some platform might need do minor change to the shared code.
In order to support this case, this patch updated the build tool
to generate a macro definition for current build platform name
in a header file. so the shared code could have platform specific
code change with this macro definition.
e.g. add "#define #define PLATFORM_ADLS 1" for ADLS.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [ADLS] update
FspsUpdUpdateLib could be shared by different platform,
use ADLS macro definition instead of PcdAdlLpSupport for
ADLS specific change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
SBL uses PcdMemoryMapEntryNumber to control the max entry
number of memory map info HOB. In some platforms, CML
encountered "Memory map failure" due to the actual entry
number exceeding it. So increase the max to accommodate
the case.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch fixed build issues caused by adding L2QosEnumerationEn UPD
which is not present on other ADL platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The default big core number was set to 8, it has to be overridden if
the CPU number is not 8. Had better set to 0xFF to all active big cores.
Also it mentioned the default value is 0xFF in the help message.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Unlike ADLS, TSN link speed will be coming from the Cfg data.
New TSN GPIO table needed for ADLN board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous commit fe6cf3272 unexpectedly changed the AUTO payload-switching
behavior. This patch restores the behavior to the original design.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Add PchPseAicEnabled and PchUnlockGpioPads in
CfgData_Silicon.yaml file to allow modification
using Config Editor tool.
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Some of the RTCT table entries werent populated due to this
missing UPD setting. Hence, assigning it to the correct value.
TEST= Verified the fix on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch adds control option for TCO timer.
Use case: the control option shall be enabled when Linux hw watchdog
driver (iTCO) is enabled.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added a new 64bit base field in the loader serial
port hob to support 64bit resource. The revision is updated
to 2. It is backward compatible with revision 1.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds "fs load" command to SBL shell so that it can be
used to load a file from boot media into memory. It also supports
loading file at specified memory address.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Graphics driver in FSP Silicon init is expecting
board related changes for VBT, so moved UpdateVbt
function call before Silicon Init.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Removed RTC logic, it is problematic and should not be used,
all other platforms are not using this logic and
we should remove this from the code
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch added support for ADLN platform.
EC related ACPI changes need to be reinvestigated
as disabling ECAvailable NVS change might be
sufficient to disable EC support in ACPI.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch enables graphics console when entering FWU payload.
FWU progress will show on both graphics console and serial port.
Signed-off-by: kokweich <kok.wei.chan@intel.com>
This patch fixes the test case where when a bad dso is
provided, it will revert back to the default dso settings.
TEST= Ran the test case successfully on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
On TGL, Linux reported ACPI errors on missing PRES method for SATA
port 0. This patch added the missing PRES implementation for all
SATA ports.
This fixed#1497.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL ACPI table does not define any I2C pad or panel. And
it will cause ACPI error for Linux. This patch added conditional
scope for I2C pad and panel reference so that if pad type or panel
type is not defined, these scope will not be used by ACPI.
This fixed#1496.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Fix two errors:
ACPI Error: Aborting method \_SB.PR00.GCAP due to previous error
(AE_INVALID_TABLE_LENGTH)
ACPI Error: Aborting method \_SB.PR00._PDC due to previous error
(AE_INVALID_TABLE_LENGTH)
UEFI BIOS always does dynamic loading, but SBL does static loading
instead.
Signed-off-by: Randy Lin <randy.lin@intel.com>
As part of FSP updates for ADLPtest board, update
Silicon UPD settings.
TEST=Validated boot on the RVP board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
With latest changes for S0ix, PciePm is expecting GetCpuSku and
GetCpuSkuInfo function declaration in header files. Added these
declarations in CpuPcieHsPhyInitLib header file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-S.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for ADL.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
This patch enable S0ix feature in ADLP
1. Ported correct NVS value for ADLP.
2. Ported ACPI value refer to BIOS.
3. Implemented workaround for RP08.
Verified: ADL-P RVP
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Current TGL platform set 0 as the PCI end bus number in ACPI
MCFG table. And it caused incorrect MMCONFIG range calculation in
Linux. This patch updated the template to use 0xFF as the PCI
end bus number.
It should fix#1481, to be confirmed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-s.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for TGL.
Verified: TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch adds Platform and Silicon support for Alderlake
project. Currently, FSP and microcode are not publicly
available. So build will fail with errors. We will update
the project whenever they are available.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
s0ix feature enabling flag also turn off some FSP configs
so that default SBL image can't detect the onboard Lan
and type c devices.
Signed-off-by: Randy Lin <randy.lin@intel.com>
This patch enhanced GPIO convert tool so that it can handle the
new GPIO template format.
EX:
To convert GPIO from YAML format to CSV format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
Platform\ElkhartlakeBoardPkg\CfgData\CfgData_Gpio.yaml
-of csv -o gpio.csv
To convert GPIO from CSV to YAML format:
python Platform\CommonBoardPkg\Tools\GpioDataConvert.py -cf
Platform\ElkhartlakeBoardPkg\Script\GpioDataConfig.py -if
gpio.csv -of yaml -o gpio.yaml -t new
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes no activity on UART0 pins when enabling it for serial
communication.
In TGL, there are two UART0 instances (GPP_C8~C11 and GPP_F0~F4) while
one (GPP_F0~F4) is shared with CNVI. This patch enables GPP_C8~C11 as
the UART0 instance to reduce the conflict with CNVI.
This patch also fixes the GPIO pins definition for TGL-H and moves
serial io initialization code to SerialIo.c to simplfy Stage2BoardInitLib.c.
Test: TGL-UP3 RVP and TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
1. Update VERINFO_PROJ_MINOR_VER to 3 for MR3
2. Update PSE SIZE to 0x00030000
3. Removal of PchCpuTempSensorEnable FSP UPD due
FSP update
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Increase CFG_DATABASE_SIZE due to the addition
of up6000 dlt file in SBL EHL cfgdata.
The AddConfigData funciton will return EFI_OUT_OF_RESOURCES
due to insufficient cfgdata size when TCC is enabled.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
IsMarkedBadDso and InvalidateBadDso would be required for all
the platforms that support TCC. And the implementation is also
common, so just move them to common TccLib.
Also updated the implementation to remove SPI flash erase for
InvalidateBadDso().
Signed-off-by: Guo Dong <guo.dong@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch invalidates the DSO region with a marker after
a DSO hang (caused by corrupted DSO) is detected (by WDT timeout).
With the marker, stage1b can know the DSO tuning should be skipped.
The bad DSO mark is defined as both Signature and Size in the
TCCT component header are zero.
With this patch, the previous defined WDT scratchpad bit,
WDT_FLAG_TCC_BAD_DSO, is removed.
TEST=Verified on TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Currently StitchLoader.py is under platform package, and
the common tool BtgSign.py should not depend on that tool.
And BtgSign.py indeed doesn't depend on it, so just update
it to make it could work without StitchLoader.py.
Signed-off-by: Guo Dong <guo.dong@intel.com>
On CFL and CML, the board hook PostMemoryInit was called before
FspMemoryInit API. This should be called afterwards instead.
This patch fixed this issue. It is because of missing "break"
statement. It fixed#1435.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Sindhura Grandhi