TPM is intialized by ACM with profiles 3 & 5.
This patch enables the TPM in bootloader when boot guard
is not enabled. HAVE_MEASURED_BOOT in platform
board config controls the TPM in SBL.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Added UPD Ddr4OneDpc in DLT file and removed hard coded value.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Add the hard-coded GPIO table to the header file for reference purposes.
This table is currently part of the configuration.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Without initializing CPU fan control, EC will stop CPU fan after default
timeout. This patch initializes CPU fan control and fail safe control.
Some scenarios are related to the case: (1) bootloader shell;
(2) unexpected hang; (3) OS with no ACPI support; and (4) OS fails to
load ACPI driver
Test methods:
1. monitor CPU fan under SBL / UEFI Payload shell: expect non-stop
2. check CPU fan status after Linux starts: expect ACPI controls it
Verified: TGL RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
1. Update BoardID and PlatformID for CRB board
2. Direct return after read board id from smbus to avoid boardid clashing
3. Added ddi config for CRB board
4. Update FSPM UPD due to common value across all sku
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This change makes sure that, during each recovery,
the FW update status structure is cleared and
repopulated
Without this change, in the event that there is
a full recovery and then an interrupted recovery,
the interrupted recovery is unable to resume
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
Clear the RTC EN SCI flag to avoid interrupt storming
that cause system hang when using rtcwake method to perform
powre management test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- FSP version - 0C.00.69.74
- Vbt version - 1077
- Microcode version - m_07_90672_00000023
- Minor version updated to '2' for MR2.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
- Increase PlatformMemorySize to get rid of FSP error caused
during Tcc SRAM init.
- Sort the CPUs in ascending order for Tcc validation purpose.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Use the GPIO table from SBL config data instead of
the one from .h file. the .h file will keep there
a while just for reference.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Use a on board switch (Pin B3) as the GPIO to switch
UEFI payload and OsLoader. So update its setting as
GPIO IN for this purpose.
Signed-off-by: Guo Dong <guo.dong@intel.com>
For PAD name (e.g., GPD12), current GpioDataConvert.py get the
pad number using pad_name[4:6]. It should be changed to pad_name[3:5].
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current PlatformNvs parameters are causing the power management
(S3, S4 and S5) in Windows OS. Removing the Nvs parameters will fixed
the issues.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Restore SMM registers was done in the PostPciEnumeration.
so remove the duplicated code in EndOfStages
and call ClearS3SaveRegion() in normal path to avoid
appending multiple restore records.
Signed-off-by: Guo Dong <guo.dong@intel.com>
FSP-S UPD format for THC port assignment was updated, but PEP logic
was using the old format, and causing the PEP constraint to always be
enabled. This issue didn't seem to be causing a problem, but resulted
in noncompliant low power idle constraints.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
This Patch fix the build issues due to the increased payload and image size
in windows and linux environment.
- Fixed PAYLOAD size greater than padding size issue for CML.
- Fixed FWUPDATE size greater than padding size issue for EHL.
- Fixed FV image size issue for CMLV,TGL,EHL and ADLS.
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
This patch will let ADLP project to build and stitch images from
open source.
TEST = Smoke-test to boot to Windows/Yocto
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous setting of SW-first CM mode was causing a hang during S3/S4 entry. Likely this setting requires additional ACPI/driver support which is missing.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Remove OS version check in PEPD _STA method. This is a change to the intelpep.sys ASL device (PEPD) for low power idle support. Previously, _STA would always return present/enabled for Win10 even if S0ix config flag was disabled. Changed version always returns status based on S0ix flag. Without this workaround, S4 resume was failing on ADL-N/P/PS.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Use the GPIO table for the test boards.
This change would help fix PCIe device detection from PCIe slot.
Late would change post memory gpio table to SBL cfg data.
Signed-off-by: Guo Dong <guo.dong@intel.com>
- skip the component replacemnt if the component is not located in SBL image
- print the skipped replacement components
- indicate failure through exit status for easily diagnosing problems
when checking stitch config parameters
- add required flash image region 5=EC for new FIT (15.40.26.2632)
- remove 'sata' stitch option since it is no function
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Process Gpio Cfg data from the dlt file instead of the hard-coded
GPIO table.
- The table in the PostMem hdr file is only for reference.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
The patch adds support of "GPD" group when parsing a .h header file.
It also
- adds supports for Pch-N,
- fixes leading whitespaces in h file.
Test commands:
# h to dlt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if example_adls.h -of dlt -p s \
-o out_adls.dlt
# h to yaml
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if example_adls.h -of yaml -p s \
-o out_adls.yaml
# yaml to h
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of h -p s \
-o out_h_from_yaml.h
# dlt to h
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of h -p s \
-o out_h_from_dlt.h
# check: compare example_adls.h and out_h_from_dlt.h
# yaml to txt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.yaml -of txt -p s \
-o out_txt_from_yaml.txt
# dlt to txt
$ python Platform/CommonBoardPkg/Tools/GpioDataConvert.py \
-cf Platform/AlderlakeBoardPkg/Script/GpioDataConfig.py \
-if out_adls.dlt -of txt -p s \
-o out_txt_from_dlt.txt
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
The steps of OEM key revocation are:
1. Replace OEM KM (signed with key2) by updating CSME
2. Replace BIOS region (signed with key2)
3. Reboot with new BIOS region (to make key1 inactive)
4. Revoke key1
Before this patch, it requires 2 firmware updates and 2 capsules for
step 1~2 and step 4 respectively. The patch combines them into a single
update/capsule.
To implement the feature, the patch:
1. Double max # of payloads to allow CSME/CSMD/BIOS/CMDI update
in one capsule image.
2. Prevent from failing update of a critical component.
e.g., if step 1(CSME) fails, step 2(BIOS) should be skipped
Verified cases:
Case 1: Capsule having CSMD/CSMD/BIOS/CMDI.
Expectation: successful
$ python BootloaderCorePkg/Tools/GenCapsuleFirmware.py \
-p CSME FWUpdate.bin \
-p CSMD CsmeUpdateDriver.efi \
-p BIOS new_BiosRegion.bin \
-p CMDI cmdi.txt \
...(skip)
Case 2: Capsule having CSME/BIOS/CMDI but no CSMD.
Expectation: no update
Case 3: Inject fault flow (no partition switch after first flash),
Capsule having CSME/CSMD/BIOS/CMDI.
Expectation: no CMDI update
Verification: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- update FSP version to MR4 FSP (09.04.25.11)
- update VBT version to MR4 FSP (244)
- update microcode version to 16
- update EHL platform version to 1.4
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
EHL DMA controllers are hidden at PSF level in reference code,
DMA controllers are reported as ACPI devices if ownership is Host.
So should not check DMA PCI header for DSDT table patching.
Update the change follow EHL reference code.
Signed-off-by: Gavin Xue <gavin.xue@intel.com>
When some settings from DSO caused system hang,
the WDT would cause the system reboot.
And in the next boot, SBL would use the default
setting by not apply the DSO values.
Verify on EHL CRB.
Signed-off-by: Aiman Rosli <muhammad.aiman.rosli@intel.com>
1. Ported IT8659 Sio (Super IO) and DTT (Dynamic Tuning Technology)
for ADL platform
2. Added CfgData to disable or enable the SIO feature
3. Fixed warning for Linux gcc bug -Wmissing-braces in SioChip.c
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- update FSP version to IoT FSP 5143_01_MR6 (0A.00.7B.31)
- update VBT version to IoT FSP 5143_01_MR6 (250)
- update TGLU microcode version to A4
- update TGL platform version to 1.6
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Lakkimsetti, Subash