Include in the list of supported peripherals the GPIO
and GPIOT for both the nrf5340 and nrf54l15
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Enable this test by providing an overlay for the nrf5340bsim
Both for the app and net core.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Enable this test, and provide overlays, in the nrf5340bsim
Note this test specs 2 GPIO pins to be shorted. This can be done
for the simulation target by calling zephyr.exe with the option
`-gpio_conf_file=shorts_config.txt`
Where that file would contain this one line (for the provided overlay),
for the cpunet:
---- shorts_config.txt
short 1.1 1.2
----
And this for the cpuapp:
---- shorts_config.txt
short 3.1 3.2
----
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Enable this test, and provide overlays, for the nrf5340bsim.
Both for the app and net core.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Enable this test, and provide overlays, in the nrf54l15bsim
Note this test specs 2 GPIO pins to be shorted. This can be done
for the simulation target by calling zephyr.exe with the option
`-gpio_conf_file=shorts_config.txt`
Where that file would contain this one line (for the provided overlay)
---- shorts_config.txt
short 1.1 1.2
----
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Update the HW models module to:
aeef3db9fa9e4b9d12b3bbec44f9cedc8fcb7d9c
Including the following:
aeef3db GPIO & GPIOTE: Improve notes and documentation
93549c4 UART: Fix command line parameter description
dbab746 nrf_hack: Add a few missing peripherals
4b1a61b 53 UARTE: Correct subscribe sideeffects function name
197e9cf docs: UART can be used now for 5340 in Zephyr
dc18d14 53: GPIO+TE: Add app core instances
b236c08 GPIO+TE: Add to 5340's netcore
7a621f6 GPIO: Clarify function description
1a2e1e4 GPIO+TE: Build for 54L
d121db4 nrf_gpio hal: Add new nrf_gpio_port_pin_{in,out}put_set
9bc41ce GPIOTE: Connect to DPPI
7141042 GPIOTE: Add simple support for PORT.SECURE & NONSECURE
dc930ba GPIOTE: Support having or not sense functionality per instance
a07180d GPIO: Support multiple GPIOTEs
14bdce5 GPIO: Collect status in single struct
b91da53 GPIOTE: Add support for N interrupt lines
9963424 GPIO & GPIOTE: Generalize to N instances
7379c23 GPIO+TE: Fix indentation
8d691c6 Add SPU registers stub
dd68ca9 Add NFCT register stub
cf2cc5b HW_models: NHW_NVMC: fix buffer read validation
f3db727 zephyr: module.yml: add `depends` field
09fc98f CMakeLists: remove trailing whitespace
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Refactor out the `soc_early_init_hook()` function from `pma.c` to
`soc.c` which is always compiled so that it can be extended to run
other init functions easily in the future. Then, restore the function
in `pma.c` to `pma_init()`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The function `pma_init_per_core()`, as its name suggest, should be
run from every core, so call it from `soc_per_core_init_hook()`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Allow SoC to implement their custom per-core initialization function by
selecting `CONFIG_SOC_PER_CORE_INIT_HOOK` and implement
`soc_per_core_init_hook()`.
Signed-off-by: Maxim Adelman <imax@meta.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The `soc_per_core_init_hook()` function now has `void` type after
da118b9, so it should just return without any value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This will help distinguish 64 and 32-bit platforms by tooling, following
the pattern visible in e.g. RISC-V.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
Those dtsi are a base for a range of 32-bit platforms. Setting this
compatible makes it easier to distinguish all 32-bit x86 platforms.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
y
atom.dtsi enforces "intel,x86", but it doesn't help us discern if the
platform is 32 or 64-bit. We do that for example in RISC-V and it's
useful from the tooling perspective.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
This commit updates the SSP driver to use the newly defined
SSP_IP_VER macros for IP version checks instead of relying
on CONFIG_SOC_* macros. The change ensures better readability
and maintainability by centralizing the IP version definitions
and comparisons.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Replace hardcoded register addresses and values in
asm_memory_management.h with Devicetree (DT) macros for LPSRAM
power-down operations. This change ensures that register addresses and
bank counts are dynamically obtained from the Devicetree, improving code
portability and reducing the risk of errors due to manual updates.
- Removed hardcoded LSPGCTL address definitions.
- Updated m_ace_lpsram_power_down_entire macro to use DT_NODELABEL to
fetch LPSRAM bank count and control register address
- Adjusted bit field extraction logic to align with the updated register
information from the Devicetree.
This commit aligns with the ongoing effort to utilize Devicetree for
hardware abstraction and to facilitate easier maintenance and updates to
the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the m_ace_hpsram_power_change macro from asm_memory_management.h
as it is no longer used after refactoring the power_down function to
utilize the new m_ace_hpsram_power_down_entire macro. This cleanup helps
to reduce code complexity and maintainability.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Refactor the power_down function to utilize the newly introduced
m_ace_hpsram_power_down_entire macro for shutting down the entire
HPSRAM. This change simplifies the power-down process by replacing the
previous segment-based power gating mask approach with a single boolean
flag that indicates whether the entire HPSRAM should be disabled.
The function signature of power_down has been updated to accept the new
boolean flag, and the corresponding call sites have been modified to
pass the flag based on the CONFIG_ADSP_POWER_DOWN_HPSRAM Kconfig option.
Additionally, the assembly code has been cleaned up to remove the
now-obsolete hpsram_mask array and related logic.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce a new assembly macro, m_ace_hpsram_power_down_entire, which
utilizes Zephyr Devicetree macros to power down the entire HPSRAM on
Intel ADSP ACE platforms.
This macro dynamically retrieves the HPSRAM bank count and control
register address from the Devicetree, streamlining the power-down
process. The macro is designed to iterate over all HPSRAM banks and
issue a power down command to each, ensuring a complete shutdown of the
HPSRAM when required by the system's power management policy.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit improves the readability of the power_down.S assembly file
by standardizing the indentation of the preprocessor definitions.
No functional changes have been made; this is purely a cosmetic update
to the code formatting.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit addresses an issue on platforms with an MMU where a
LoadStoreTLBMissCause exception occurs when accessing hardware registers
during the power-down process. The exception arises when attempting to
access the IPC register after HPSRAM has been powered down, leading to a
double exception: LoadStoreTLBMissCause followed by
InstrPIFDataErrorCause.
To resolve this, we preload the IPC register before shutting down
LPSRAM. This change prevents the double exception by ensuring that the
page table entries are correctly managed in the TLB before HPSRAM is
powered down and allowing the power-down sequence to complete
successfully.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
ADR status and devtime updated flags merged into an atomic bits array.
Related to Issue #55072
Co-authored-by: Jan Kowalewski <jkowalewski@cthings.co>
Signed-off-by: romain pelletant <romain.pelletant@fullfreqs.com>
Signed-off-by: Jan Kowalewski <jkowalewski@cthings.co>
Change downlink callback to transport data using flags.
Related to Issue #55072
Co-authored-by: Jan Kowalewski <jkowalewski@cthings.co>
Signed-off-by: romain pelletant <romainp@kickmaker.net>
Signed-off-by: Jan Kowalewski <jkowalewski@cthings.co>
Add definition for the Adafruit Adalogger Featherwing. This shield
compatible with the Adafruit Feather family is equipped with an SD card
slot and a PCF8524 RTC.
This work is based on the Adafruit Data Logger shield definition.
Signed-off-by: Philip-Dylan Gleonec <philip-dylan@gleonec.bzh>
Generate the Tx service request after the symbol is shifted out of the
UART. This is useful when the UART is connected to an RS485 transducer
which has a separate transmit enable gpio/line. Hence it's important
to know when the transmission actually finishes so that the drive
enable line can be disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In case the LLP wraps we need to re-read the LLPU to make sure we return
the correct value.
Suggested-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add support for realloc (and realloc_aligned) into the multi heap lib,
where the buffer sent in will either be reused (maybe shrinked),
or enlarged by allocating on any of the matching heaps of the multi heap.
Signed-off-by: Meir Komet <mskomet1@gmail.com>
Initial support for M5Statck CoreS3 development board.
Signed-off-by: Zhang Xingtao <zhxt@live.cn>
Co-authored-by: Benjamin Cabé <kartben@gmail.com>
Co-authored-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Extend the ARM M-profile suspend-to-RAM implementation to be compatible
with all versions of the M-profile supported by Zephyr: ARMv6-M, ARMv7-M,
and ARMv8-M Baseline.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Wrap the CPU register save/restore operations (GPR and special registers)
in macros to make core logic simpler to follow. This is also a preparatory
step to introduce ARMv6-M and ARMv7-M support.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Use macros to wrap the interaction between the assembly code and the
struct __cpu_context. This helps making the assembly more readable.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Remove all xPSR-related registers from struct __cpu_context, and the
associated save/restore code in S2RAM code, as they are not needed:
* EPSR and IPSR are read-only - they cannot be "restored"
* Bits N, V, Z, C, V, Q, and GE (if DSP Extension is implemented) of APSR
could be restored, but this is not needed as the AAPCS indicates these
bits to be "undefined on entry to or return from a public interface"
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Use minimized PIO code for 3-wire operation.
Input and output buffers are conventionally stored in bus byte order.
For 16 and 32 bit transfers, this is effectively big-endian, so
txbuf and rxbuf need to be read as such. Those pointers also need
to be declared uint8_t * instead of void *.
In addition, tx_count and rx_count are based on dts, and refer to
whole transfers (8, 16, or 32 bits), not bytes.
Added rpi_pico.overlay to samples/sensor/magn_polling to demonstrate
32-bit word size, and updated the README.rst to make it independent
of the specific sensor.
Clean up compliance check failures.
Fix typos.
Synchronize 3-wire TX and RX cycles.
Simplify state machine synchronization
Minimize SPI bus delay time in 3-wire mode
Move clock delay to PIO code and remove k_sleep
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
The Adafruit Feather M4 Express is a compact, lightweight
ARM development board with an onboard mini NeoPixel, 2 MiB
of SPI flash, charging status indicator and user LEDs, USB
connector, 21 GPIO pins and a small prototyping area.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
Links and the manufacturer name are updated from maxim to analog.
After the acquisition of Maxim Integrated the documentation
of these devices has been moved to the analog.com website.
Redirects exist, so they are not broken yet,
but we should not rely on that.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Links and the manufacturer name are updated from maxim to analog
for the 1-wire subsystem and the related ds18b20 sensor.
After the acquisition of Maxim Integrated the documentation
of these devices has been moved to the analog.com website.
Redirects exist, so they are not broken yet,
but we should not rely on that.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
If network interface is specified in the DNS server, then send
the queries to the server via the network interface. Print this
information in the server list.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Alberto Escolar Piedras