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soc: atmel: fix wait state value 

The datasheet specifies that 2 wait states are required at 48 MHz.

Signed-off-by: Maksim Drachov <maksim.drachov@outlook.com>
This commit is contained in:
Maksim Drachov 2024-09-04 11:48:38 +03:00 committed by Anas Nashif
parent 8084111e54
commit 91d3eb9107
1 changed files with 2 additions and 2 deletions
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4
soc/atmel/sam0/common/soc_samc2x.c
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@ -17,8 +17,8 @@
static void flash_waitstates_init(void)
{
/* One wait state at 48 MHz. */
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val;
/* Two wait state at 48 MHz. */
NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_DUAL_Val;
}
static void osc48m_init(void)