x86: Add intel,x86_64 compat to all x86-64 platforms
This will help distinguish 64 and 32-bit platforms by tooling, following the pattern visible in e.g. RISC-V. Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
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12a27f31a1
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@ -22,3 +22,7 @@
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sdhc0 = &emmc;
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};
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};
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&cpu {
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compatible = "intel,x86_64";
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};
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@ -36,14 +36,14 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,apollo-lake";
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compatible = "intel,apollo-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,apollo-lake";
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compatible = "intel,apollo-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <1>;
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};
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@ -16,9 +16,9 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "intel,alder-lake";
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compatible = "intel,alder-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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@ -16,7 +16,7 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,apollo-lake";
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compatible = "intel,apollo-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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@ -16,7 +16,7 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,elkhart-lake";
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compatible = "intel,elkhart-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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@ -15,7 +15,7 @@
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#size-cells = <0>;
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cpu@0 {
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compatible = "intel,raptor-lake";
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compatible = "intel,raptor-lake", "intel,x86_64";
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device_type = "cpu";
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d-cache-line-size = <64>;
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reg = <0>;
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@ -16,7 +16,7 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,raptor-lake";
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compatible = "intel,raptor-lake", "intel,x86_64";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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