USB2 port 8 (index 7) is connected to MCU on UPX board. It does not
respond to USB enumeration. The original code disabled port 10, but
it should be port 8. This patch fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed incorrect GPIO pin used for BOM ID detection for
UPX board. It also fixed the incorrect RX bit within GPIO CFG DW0.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added required code flow to prepare to enable DMA
protection for CFL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For CFL, VT-d PMR cannot be fully enabled
before FspSiliconInit. So it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added required code flow to prepare to enable DMA
protection for APL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For APL, since VT-d is only enabled
in FspSiliconInit, it was postponed to Stage2.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
By default 4MB was allocatd for OS crash mode support. Hoever, no
project is really using it at all. The default should be changed
not to reserve any memory for it. For platform needs it, it can
override using platform specific CFGDATA.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added the VTd PMR memory protection library. It can be
used to support DMA memory protection feature later on. It also
enabled basic build on APL platform so that it can be tested as part
of the automatic build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since SgxLib has a dependency on platform
specific FSP header files it should not be
used as a common platform library. This
patch preserves the same functionality as
before but just moves the library to be
silicon specific.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
When USB devices are used to wake from S3 and S4, PME_B0_STS
GPE bit is set and is causing SMI storm which is resulting intel
board hang during wake from S3 and S4.
Clearing PME_B0_EN during wake helped fix the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added ACPI WMI based firmware update trigger interface
for QEMU. It provides standard interface for SBL to trigger firmware
update.
If with SBL sbl wmi driver integreated, use the following to trigger
FWU:
echo "1" > /sys/bus/wmi/devices/44FADEB1-B204-40F2-8581-394BBDC1B651
/firmware_update_request
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PciEnumeration() scans a single PCI root bridge currently.
The PCI_ENUM_POLICY_INFO structure will be generated at build time,
and this will allow PCI enumeration more flexible.
typedef struct {
UINT8 DowngradeIo32;// default:1
UINT8 DowngradeMem64; // default:1
UINT8 DowngradePMem64;// default:1
UINT8 Reserved;
UINT8 BusScanType; // default:0 (0: list, 1: range)
UINT8 NumOfBus; // the number of BusScanItems
UINT8 BusScanItems[0];
} PCI_ENUM_POLICY_INFO;
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added code to:
- Trigger FWU using sticky register in SBL Shell
- Detect FWU mode using combination of sticky register and state
machine
- Clear the trigger flag at the end of FWU
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added some basic test script for QEMU. It can be
used by travis to do some test automation for PRs.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added a script to test QEMU firwmare update flow.
To use it:
- Build SlimBootloader.bin for QEMU
python BuildLoader.py build qemu
- Generate firmware update capsule
python BootloaderCorePkg\Tools\GenCapsuleFirmware.py
-p BIOS Outputs\qemu\SlimBootloader.bin
-k BootloaderCorePkg\Tools\Keys\TestSigningPrivateKey.p
-o Test\FwuImage.bin
- Run the script
python qemu_fwu.py Outputs\qemu\SlimBootloader.bin Test
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
With EDK201911 BaseTools update, a ACPI binary is not included into ACPI
table section properly and it mis-leads some other ACPI tables as well.
This will add 'RAW BIN' type in ACPITABLE override rule and use it for
ACPI binary integration into ACPI table section.
Signed-off-by: Aiden Park <aiden.park@intel.com>
FPDT size should be FIRMWARE_PERFORMANCE_TABLE. And updated
this logic to correct the size and adjust next ACPI table
starting address.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch printed out the loaded data from the test containere.
It is helpful for tool to parse the boot log and verify if the
component inside the container has been loaded properly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are many parameter passing to AcpiPatchPssTable().
A single PSS_PARAMS structure pointer will be passed to simplify.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will allow update PSS table in a common way.
For a platform specific power calculation,
a function pointer can be provided.
Signed-off-by: Aiden Park <aiden.park@intel.com>
- Update of comment in Fwst.aslc for coffeelake as per review comment.
- Update of comment in Boardconfig.py for qemu.
- Removal of vtf0.bsf in BootloaderCorePkg.
Signed-off-by: SM <s.m.narayanan@intel.com>
This patch added following enhancement to GenContainer script:
- Fixed python3 errors in some specific condition
- Added more error handling to notifce the user on failure
- Removed -od option and use directory of -o option instead
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In GenContainer tool auth definitions for RSA cases were
updated to include hash alg used. In current implementation
auth type is generated from hash type and private key while
container created. This patch removes hash type param
and auth type is used for hash alg generation.
Platform code to be updated as per updated auth definitions
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Configuration data blob is supported only from Bios region.
Removing CfgData in PDR as its no longer getting used.
Updated to copy signed data structure length for max supported.
Max supported is for RSA3072 size.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch does the following
1) Enable triggering firmware update from OS
2) When firmware update mode is given control, state machine
is set to capsule processing and firmware update platform
specific trigger is cleared. State machine will be used
hereafter to track firmware update
3) Created CheckStateMachine method in BoardSupportLib.c to
check state machine to see if firmware update is in progress
and set boot mode to firmware update.
4) Removed CMOS way of triggering firmware update and wrote code
to use Over-Clocking WDT Scratchpad (OC_WDT_SCRATCH) bits for
triggering firmware update
5) Update shell fwupdate command to use OC_WDT_SCRATCH bits.
6) Removed extra reset during sbl firmware update
7) Removed reset after updating configuration data update
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Hash and RSA signing parameters were hardcoded in
Crypto wrappers and secure boot libraries. This patch
address support for multiple hash and key sizes.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
Current SBL hash store has many limitations:
- Only support fixed hash size
- Only support 1:1 public key and usage mapping
- Only support build time key enrollment
This patch addressed this issue by introducing:
- Add a updatable KEYH component to hold extra key hash
- Allow append new hash entries from KEYH
- Use variable length entry for hash
- Introduce "Usage" bit mask for a key usage
This will allow using a single key to sign multiple components, or
using multiple keys to sign a single component. The built-in hash
store will only contain hash for STAGE1B, STAGE2, PAYLOAD,
PAYLOAD_FWU and MASTER public key hash. Master key hash will be used
to verify the KEYH component loaded at runtime in Stage1B. Once KEYH
is loaded, it will be appended into global hash store. The combined
hash store will be used to verify other components on the boot flow.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch updated the PayloadId detection logic on APL platform
to make it easy to understand.
The current policy is as below:
- If PayloadId CFGDATA is not AUTO, use whatever provided in CFGDATA.
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is enabled, uses GPIO level to determine the actual PayloadId to
use. (HIGH:OsLoader LOW:UEFI)
- If PayloadId CFGDATA is AUTO, and GPIO based PayloadId detection
is disabled, uses default PlatfomrId 0 (OsLoader).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The previoius IPP library updates used UpdateSHA256V8 as default for
SHA256. It works on real platform. However, QEMU's default CPU config
does not support SSE3 instructions and will generate exception. This
patch added the UpdateSHA256Compact as default SHA256 function if no
advanced optimization flags are set. The same is applied for SHA512
functions too.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
AVX(G9) and SSE4(W7) is added to IPP crypto lib.
PcdCryptoShaOptEnabled is added to enable optimzations
in IPP SHA256 and SHA384.
Default is set to V8 (SSE3) for SHA256. ENABLE_CRYPTO_SHA_OPT has to
be configured in Platform board config files for optimizations
to be enabled.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
PcdDebugInterfaceFlags and PcdDebugOutputDeviceMask are defined
for debug devices, so removed PcdDebugInterfaceFlags.
Add a new PCD PcdDebugPortNumber to indicate the serial debug
number.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added WMI service in ACPI to provide a unified mechnism
for user to trigger a firmware update flow. New ASL methods are
defined. \DWMI.WQ00 is for read and \DWMI.WS00 is for write.
To use it from Linux (Ubuntu):
- Install acpi-call module
sudo apt install acpi-call-dkms
- Load module
sudo modprobe acpi_call
- Read trigger register value
echo '\DWMI.WQ00 0' | sudo tee /proc/acpi/call
sudo cat /proc/acpi/call
- Write trigger register value
echo '\DWMI.WS00 0 0x12' | sudo tee /proc/acpi/call
To use it in Windows:
- Open a command line window with admin right.
- Run VB script to read / write the trigger register
set Service = GetObject("winmgmts:root/wmi")
set EnumSet = Service.InstancesOf ("AcpiFirmwareCommunication")
for each Instance in EnumSet
Wscript.Echo "Current Val: " & Hex(instance.Command)
instance.Command = 1
instance.Put_()
Wscript.Echo "Set New Val: " & Hex(instance.Command)
next 'instance
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL currently set IA Untrust bit in MpInit(). It is too early for
BSP. By doing so, it blocked some register access in FSP notification
APIs. This patch moved the IA Untrust bit set for BSP to the end of
boot flow while keeping it at same location for APs.
It also fixed#466.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL calls ClearFspHob() too early. Since HOB is required
during the whole FSP life cycle. It is better to clear it at the
end after the last call. Otherwise, some previous API call will
potentically encounter issues.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This is a follow-up to the previous WOL commit. The previous
implementation is more LeafHill specific. This patch further
added configuration data to control how wake up signal is mapped
into each PCIE root port. And the ASL code has been adjusted to
utilize that info so that the code can be more generic for all
other platforms.
The current default configuration for PCIE wake signal is aligned
with LeafHill CRB board. For other borads, to enable it properly,
it is required to override the wake signal configuration using DLT.
Test has been done on LeafHill to do WOL with yocto image. It worked
as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added export sub-command support in CfgDataTool.py. It
is useful for users to export external CFGDATA from an exising
BIOS or IFWI binary file.
EX:
python BootloaderCorePkg\Tools\CfgDataTool.py export
-i Outputs\cfl\SlimBootloader.bin -o Temp
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added additional information in the GPIO CFGDATA header
structure so that the full GPIO info can be extracted out later on
by tool. This additional information including GPIO SKIP bit position,
GPIO ID position and length.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL has platform specific GetBuiltInConfigData() implementation
because the internal CFGDATA blob is embedded into Stage1B data section.
Instead, it can be put into Stage1B FV FFS file, and then use a PCD to
get the base. In this way, it can be handled directly in core code and
remove platform specific implementation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
MRC re-init happens in next boot when an warm reset is issued in MRC
fast boot path. DRAM Initialization Scratchpad Bit is one of warm reset
detection logics, but the bit is not updated at fast boot path.
Signed-off-by: Aiden Park <aiden.park@intel.com>
OsBootOption config data provides addendum field to support multiple boot
option config data into a single boot option.
This patch updates a single boot option properly with multiple addendums.
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
UEFIPayload uses SMM dispatch for Physical Presence (Tcg2SMM) SMI.
Updated SMI port usage in asl to trigger SMI registered for
Physical Presence operation
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
GenGpioData.py is a utility that converts
GPIO pin data from one format to other.
The formats currently supported are [h, csv, txt, dsc, dlt].
[h, csv, txt] formats are external to SBL and [dsc, dlt] formats
are known to SBL. So, this tool provides a way to convert one
of the [h, csv, txt] to [dsc, dlt] and vice-versa.
Example usage:
python GenGpioData.py -if GpioInput.csv -of dsc
python GenGpioData.py -if GpioInput.dsc -of txt
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
ConfigEditor.py tool reports a warning regarding the
incorrect Interrupt Configuration for pins on Upx boards.
Certain board's default PAD CFG values may have none of
NMI/SMI/SCI/IOAPIC set and also RXEVCFG set to Disable,
so add a corresponding option in the drop-down for IntConfig.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Currently, only absolute path is allowed in '-w' stitch_dir and '-s'
stitch_zip file. In addition, if stitch_dir is not absolute path, the
stitch tool looks for 'SBL_SOURCE' which does not exist in OS environment.
This patch allows the StitchIfwi.py tool to use relative path as well.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Added a option in CFL StitchIfwi script to pass the TPM type to
be selected for Intel FIT tool stitching.
[TEST] = Run StitchIfwi.py with -tpm=dtpm for WHL
and verify use of dTPM.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
BootPolicyManifest are required when a IFWI is
stitched with Intel BootGuard enabled. FlashMap maintains a pointer to
it so that SBL code can reach to them during execution.
This patch removes the check for its presence from IFWI images.
Test : Stitches Ok. Boots Ok.
Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com>
This patch is a follow-up patch of #380. If a platform disables HS400 mode,
silicon init code will configure eMMC in HS200. Other modes not in scope.
This will also fix#406.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows a board to configure XDCI mode.
By default, keep XDCI mode as PCI mode which is default value in FSP.
The mode can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 2 > Enable XDCI
If XDCI mode needs to be overrided, put new value in .dlt(delta) file.
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x0 (Disabled)
- DEV_EN_CFG_DATA.DevEnControl2.XdciEnable | 0x2 (ACPI mode)
It will fix#397 with the override value in a delta file.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch changes the default behavior of gpio pin for payload
selection, currently user configured GPIO pin being high boots
to uefi payload, modified code will boot to OS loader when GPIO pin
is high.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
power button 4 second press will cause power button override
bit to set in PM1 status register, this bit is not cleared on
reset and is causing SMI storm during booting to OS.
Power button override bit if set is cleared now in stage1b and
this fixed the SMI storm issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code set payload id depending on the gpio settings
and user selection from configuration data. When UEFI payload is
selected using GPIO or config data, payload id is being set to
UEFI irrespective of boot mode, which cause notification function
to get called, this locks the spi which inturn fails firmware update
Modified code to set payload id only in non-firmware update boot mode.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
UPX board has different memory configurations indicated by GPIO pins.
This patch added GPIO detections for these pins and set it as BomID.
It can be used to decide which SPD data to use later on.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted power related UPD settings to BIOS
UPD values are configurable through configuration data
After these changes, CPU maximum operating frequency
increased from 3.7GHZ to 4.2GHZ on WHL.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This is to fit the size of the latest Debug UEFI Payload.
Increase the size from 0x00180000 to 0x00190000.
Signed-off-by: Aiden Park <aiden.park@intel.com>
StitchIfwi.py supports '-q' parameter to enable SPI QUAD mode.
However, it does not work as expected. When the script tries to
modify the XML file, it used 'yes' and 'no' as option values.
But it is case sensitive, and should use 'Yes' and 'No' instead.
This patch fixed this issue.
Test was done on LeafHill board and it enabled SPI QUAD mode
in IFWI after the fix. It fixed#370.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
mShellCommandCse is not defined in CoffeelakeBoardPkg so can't extern.
It is not either used in current context.
Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
This patch switched to use SerialPortLib in BootloaderCommonPkg for
QEMU and CFL platforms. For APL platform, it can also use this common
library. However, it has an optimized SerialPortLib with FIFO enabled.
So for APL, it still uses its SOC specific library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The WHL(and CFL-R) has its own SpiFlashLib, but it's almost identical
to common SpiFlashLib except of silicon specific part.
Therefore, CoffeelakePkg will have its own PchSpiLib and re-use common
SpiFlashLib.
- Remove CoffeelakePkg SpiFlashLib and related files
- Use commmon SpiFlashLib
- Use CoffeelakePkg SpiFlashLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
QEMU has its own SpiFlashLib and SpiFlashLib.h file.
But, the header file is identical to the one in Silicon/CommonSocPkg.
Therefore, remove QEMU's one and re-use the common header file from
Silicon/CommonSocPkg.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL after booting to Windows, SCI interrupt storm was seen due
to GPE event 111 (2-tier GPE event). This event needs to be handled
when RTD3 table is implemented. However, current code has _L6F
ASL code without RTD3 table. This causes the SCI event to be enabled
in Windows. Since there is no real handler to clear the SCI event,
SCI interrupt storm will occur. This patch commented out the _L6F ASL
method.
Tested this on WHL. The CPU utilization drop down from original 10%
to close to 0% for system interrupts.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Add support to load the boot image from container.
Container must be signed using the same private key
as the key used to sign IAS (i.e. IAS_PRIVATE_KEY).
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current logic enables all EN bits in PMI_EN in order
to clear single PWRBTN_EN bit. This should not happen.
Corrected the logic so that only PWRBTN_EN is cleared and
the other EN bits are untouched.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
On UP Xtreme board current code only supports PCH UART debug port.
But this board has two extra UART ports behind SIO chip F81801.
This patch added required initialization for the SIO chip to enable
UART on SIO. It can be enabled through platform data during stitching.
For exmaple,
"-p 0xAA000210" parameter in stitching will select PCH UART2.
"-p 0xAA00FF10" parameter will select SIO COM1 as debug device.
"-p 0xAA00FE10" parameter will select SIO COM2 as debug device.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
GenContainer.py tool can be used to create a container
with the boot files as follows:
python %SBL_ROOT%\BootloaderCorePkg\Tools\GenContainer.py create
-cl CMDL:<cmdline.txt> KRNL:<vmlinuz> INRD:<initrd>
-o <Out> -k <Key>
<cmdline.txt> = command line file
<vmlinuz> = kernel image
<initrd> = initrd image
<Out> = dir/file where final Pods Image is copied
<Key> = Private signing key file/dir path
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current ConfigEditor only supports UINT8 format cell in table.
This patch added support for variable cell width including UINT8,
UINT16, UINT32 in table widget. Test configuration items were
also added in QEMU to test these format.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
QEMU compiling will fail when EXECUTE_IN_PLACE is set to 1 due to
size issue. Even after fixing size issue, the execution will still
fail. It is because the variable services will try to put SPI into
command mode while code fetching will fail if it is executed from flash.
This patch added necessary code to skip variable tests in Stage1B and
Stage2 when XIP is enabled. It fixed#324.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch provides the basic infrastructure to add a
Debug Port Table 2 (DBG2) to specify one or more ports
for debugging purposes. More info reg DBG2 @ :
https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn639131(v=vs.85)?redirectedfrom=MSDN
If the platform wants to report a debug port to Windows,
it should patch the DBG2 template provided with the
corresponding debug port information. And this updated
DBG2 must be referenced in RSDT.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch will change the code to always use absolute path
for stitching zip file, if relative path is provide, code will
convert it to absolute path.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
In order to make ACRN to boot, it is required to set boot from eMMC
RAW partition 1. However, current boot option is set to 0, which
caused the boot failure. This patch updated the SwPart to 1 and filled
the LBA with expected format. It fixed#317.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current Gpio config provides a way to select PadMode. But
Native Functions for a PCH are just numbered #1,2, etc. and
do not provide enough information for the end user while
configuring the PadMode.
This patch adds the required Native Function information help
strings in the drop down menu while configuring the PadMode.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This will detect CPUs up-to 255 and update MADT ProcessorLocalApic entries
with the detected CPU information.
- Set PcdCpuMaxLogicalProcessorNumber to 255 in QEMU BoardConfig.py
Test>
qemu-system-x86_64 -machine q35 -nographic -serial mon:stdio
-pflash Outputs/qemu/SlimBootloader.bin
-smp 8
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added support for CFLS and CFLH stitching by patching
proper xml file for the platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Currently in Stage1B it defined gpio table for pre-memory, but no one
program that gpio table. This patch adds it.
Move full GPIO table program from Stage1B to Stage2
Remove unused global variable mRsvdSmbusAddressTable in Stage1B.
TEST= Build success.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch will patch parameters for BpmGen2
based on the example file provided in the BpmGen2
package.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch will use a list of xml changes required and
patch them in a loop rather than patching each change
seperately.
This patch also add parameter to indicate platform for which
ifwi is getting build.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch will remove FitHelp.py dependency from StitchIfwi
and reuses code from IfwiUtility to patch ACM binary.
This patch also fixed some case dependency required for python
in xml file patching. without this fix, fit does not work as
expected.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Klocwork scanning reported several issues in the
PayloadPkg and Platform code folders, this commit
aims to resolve all of the issues currently being
reported in these folders.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
TpmSsdt.asl is common for supported platforms
SMIE for SMI control access is defined in Platform DSDT
for CFL and APL.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This patch will seperate SPD config data from memory configuration data,
as a small change in the SPD config data is resulting in duplication
of the memory config data. After sperating SPD config data, duplication
of whole memory cfg data is not required and would result in saving space.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Some misc enhancements for build scripts including:
- Adding all required exectuable check for build
- Removng hardcoded Python27 path
- Printing out used python version and path
- Using EDKII stable201905 tag to build QEMU FSP
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch cleaned APL and CFL stitching script.
- Shared common code for stitching functions on flash map process
- Converted coding style to snake_case for consistent naming convention
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
EDK II build has enabled python3 support. Since SBL has its own scripts,
it is required to port them accordingly to support python3. This patch
added python3 build support for SBL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added detailed flash map print in BIOS region for WHL
stitching script StitchLoader.py. In this way the script will
have consistent print format as APL.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Users might want to have some parameters that can be set
from UEFI environment. UEFI NVRAM variables provide a way
to achieve this functionality. And they require these vars
to be read from bootloader.
This patch provides a library to get read access to the
UEFI variables stored in NV region. The driver was ported
from MdeModulePkg\Universal\Variable\Pei @ EDKII Open Source.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Update TpmType to LoaderPlatform info hob based on
Type updated in Platform Info. LoaderPlatformInfo revision
is updated.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
Getting platform name from config data and set platform name is
common almost for all the platforms. So move it to common library.
Loading external configuration data from SPI is also common, so
add it into common library. Platform could still use its own method
to load config data if the common one doesn't work.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Update the indices for Dw0, DW1 in Gpio Template after
the PinOffset Dword has been removed in the previous commits
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current code will check if the first 4 bytes of the existing
MRC training data, if it is 0xFFFFFFFF then MRC training data
will be saved otherwise even though there is change in the
training data, it will not be saved.
Modified the code to compare the incoming training data to the
saved data, if they do not match, save the incoming training data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
To make it easier to share the most common configuration items in a
DLT file, it is better to support '!include' in DLT file. This patch
added this feature. It also added examples in QEMU to test this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled Linux as payload support on QEMU platform. To build
Linux as payload, please follow instructions mentioned in commit:
4a5af4f8b0
In addtion, to boot Linux payload on QEMU, please append following
into QEMU command line to set Payload ID to 'LINX' dynamically.
-boot order=abc
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Because of an error in Stitchloader.py, input file
slimbootloader binary data is not patched to the input
Ifwi. This error is now fixed which will produce correct
Ifwi image.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch will add support for StitchIfwi.py to generate
Boot Guard enabled IFWI images for WHL/CFL platforms
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
PinOffset information like PadNum, GrpIdx for a GPIO can be
adjusted in the fields available in DW1, where as ChipsetId
can be determined dynamically. This reduces the config data
size significantly. So, we can remove PinOffset info i.e. the
first dword in the GpioTableData.
Moved static definitions to top of the file in Stage2 board init.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
The current implementation used a huge array to represent boot options in
a single CFGDATA tag. With this approach, when a different board needs
to modify a single field, the whole array needs to be duplicated in the
CFGDATA. It is not efficient. A better approach is to break the options
into individual boot option CFGDATA tag. It will reduce the overall CFGDATA
in general. This patch implemented this mechanism. A library interface
FillBootOptionListFromCfgData() is provided to convert the CFGDATA into
the required OS_BOOT_OPTION_LIST.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled very basic support to boot UP Xtreme (URL:
https://up-board.org/up-xtreme). Lots of porting are still required.
At this point, it can boot to OsLoader shell on PCH debug UART2 on
UP Xtreme board. It can also boot Ubuntu 18.04 and Yocto image.
Since there is no board ID check for UPX board, fixed Platform ID needs
to be specified during stitching. Here 0x10 is used for UPX Platform ID.
EX:
python Platform\CoffeelakeBoardPkg\Script\StitchLoader.py -i
XtremeBios.bin -s Outputs\cfl\SlimBootloader.bin -p 0xaa000210 -o ifwi.bin
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
S4 resume sets PWRBTN_EN. And since SCI_EN is set to 0,
this situation will generate spurious SMI# once GblSmi
is enabled.
Also moving RestoreS3regs before ProcessAllLocks, as SMI_LOCK
setting will prevent enabling GblSmi on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
EOS bit set issues are fixed in SBL. Removed the
work around done for setting EOS before SMI
is triggered.
Signed-off-by: lsubash <subashx.lakkimsetti@intel.com>
This patch enabled container use case for EPAYLOAD loading.
It also switched to use LoadComponent() API for Stage2 and
payload loading. It simplified the code flow. An example in
QEMU was added to demonstrate on how to add a container in
build and load it in Stage2 code.
To define a container layout, it is required to provide
GetContainerList() in BoardConfig.py. Then in stage or payload
code, LoadComponent() can be used to load a component from the
container.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Mender is an A/B partitioning scheme
for Linux OSes. Adding initial support
for specifying the root partition label
that should be used. Later on the root
partition label should be acquired based
on the value of the env files stored in
the EFI/FAT32 partition of the boot media.
Also fix misspellings.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When writing flash in SMM mode, some platform need disable SMM write
protection. when this flag is set, it means this platform need disable
SMM write protection.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
- Revert 'Determine Firmware Update boot mode at post tempram exit #210'
- Enable SMI on S3 resume path ONLY with UEFI payload
- Move EnableSmi from PrePciEnumeration to EndOfFirmware
Signed-off-by: Aiden Park <aiden.park@intel.com>
Same GpioPinOption is used in PID selection and Payload selection.
Re-use GpioPinOption in PIDGPIO_TMPL template as well.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Config data should offer a full list of GPIOs for the
end-user to be able to select for PlatformID.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Generate NHLT(Non HD audio Link Table) depending on CFGDATA
- Add HDA_CFG_DATA for HDA and NHLT
- Create NHLT depending on config data value
HdaLib is from edk2-platforms devel-IntelAtomProcessorE3900 branch.
- Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
- Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/
Include/Private/Library/DxeScHdaNhlt.h
Include/Private/Library/ScHdaLib.h
Include/Private/ScHdaEndpoints.h
Private/DxeScHdaLib/ScHdaEndpoints.c
Private/DxeScHdaLib/ScHdaLib.c
ScInit/Dxe/ScHda.c
Signed-off-by: Aiden Park <aiden.park@intel.com>
Issue:
The Bios.xml generated from StitchIfwi.py is referring to Stitch_PROV.bin.
But the SBL Output Stitch_Components.zip contain instead Stitch_FB.bin.
Fix for issue #224:
Consistently use input file names for IFWI stitching, by chosen for 'FB'
instead of 'PROV'.
Signed-off-by: Markus Schuetterle <markus.schuetterle@intel.com>
Move Intel(R) SGX library to CommonBoardPkg, except for the config.
This is because Intel(R) SGX library is common for all platforms that
support Intel(R) SGX (Intel(R) SGX is available on all platforms
starting 6th generation Skylake).
Config is specific to each platform since options can vary from platform
to platform.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Fix typecasting bug in IsSgxFeatureCtrlSet()
Fix BOOLEAN typecasting bug in IsSgxFeatureCtrlSet() and add DEBUG_WARNs
when certain checks fail.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Add microcode patch for CFL-S A stepping
Microcode patch for CFL-S A stepping was missing.
This was causing an issue with enabling Intel(R) SGX even when it was
enabled in the config. Hence, added the patch.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
Remove the requirement for the end user to know
community, group etc. And just expose GPIO pins
to select to program PlatformID.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Below items have been changed.
- Capsule device instance index from 5(range 0-3) to 0
- Set default value for PCIE RP Power/Reset pin even if it's disabled
- Maximum GPIO alternative mode number from 3 to 5.
It fixed#204.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently, pcie clock configuration has fixed values while updating
FSP-S UPDs.
Added a capability to use PCIE CFGDATA for pcie clock configuration.
Additionally, PCIE config page/sub-pages hierarchy has been updated.
Old: Silicon Settings
- PCIE RP Config Data
New: Silicon Settings
- PCIE Config
- PCIE RP Config
- PCIE Clock Config
Signed-off-by: Aiden Park <aiden.park@intel.com>
The PCIe Root Port utilization for GP MRB is:
RP0 - /
RP1 - /
RP2 - CFB I210
RP3 - CFB M2 Cellular
RP4 - I210
RP5 - BT/WIFI
CFB = Customer Feature Board
Issue:
PCIe device BT/WIFI was not enumerated.
This corrects the complete PCIE_RP_CFG_DATA configuration
for the GP MRB board.
Signed-off-by: Markus Schuetterle <markus.schuetterle@intel.com>
ConfigEditor returns a warning in GPU Config page.
WARNING: Value '2' is an invalid option for 'InternalGfx' !
Update InternalGfx from 0x02 to 0x01 !
The InternalGfx does not provide proper options and its default value
must be '1' or '0' instead of '2'.
Additionally, renamed 'GPU Config' page name to 'Graphic and Display'
and also removed unnecessary sub-page 'GPU'.
Signed-off-by: Aiden Park <aiden.park@intel.com>
EC_SMI_N GPIO pin is currently not being used by Slim Bootloader.
But configuring this will cause spurious SMIs to occur when EOS
is set in the payload.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current default GPIO payload ID selection is UEFI on APL platform
since the GPIO pin is high without any jumper set. This patch
changed the default paylod ID to OsLoader when the GPIO is set to
high.
It fixed#208.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is a invalid value(8MB) in CfgData_Memory.dsc which causes
an WARNING when opening memory setting in ConfigEditor.
WARNING: Value "8388608" is an invalid option for "TsegSize" !
Update TsegSize from 0x00800000 to 0x01000000 !
In FspmUpd.h description, Tseg Size is "0x400000 for Release build
and 0x1000000 for Debug build".
Tseg size 4MB(0x400000) is enough with SBL regardless of build type.
Therefore, let's remove config option and use fixed size(4MB) simply.
It fixed#205.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Whiskeylake platform contains memory SPD data in memory configurations.
Since it has 4 SPD tables, loading is very slow in ConfigEditor. The SPD
table can be broken down into individual page for display to enhance the
loading performance in ConfigEditor.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows to use one GPIO pin to select different Payload ID.
When enabled, if GEN_CFG_DATA.PayloadId is set to 'AUTO', the GPIO pin
low level will select OsLoader payload, and high level will select UEFI
payload. If GEN_CFG_DATA.PayloadId is set to other values, the GPIO pin
low level will always select OsLoader payload, and high level will
select the Payload ID specified by GEN_CFG_DATA.PayloadId.
On APL LeafHill, OxbowHill and JuniperHill boards, the current GPIO is
set to GP48 (Pin 10 on J6B2 connector). This GPIO pin should be used as
input signal, and can be reconfigured for alternative functions after
the Payload ID selection is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows payload ID selection toggling using GPIO. When
the payload ID is set to "AUTO" in CFGDATA, the actual payload ID
will be updated according to current GPIO level. If the GPIO is low,
the payload ID will be set to 0 to boot OsLoader/FwUpdate payload.
If the GPIO is high, the payload ID will be set to 'UEFI' to boot
UEFI payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When SBL calls board notification ReadyToBoot and EndOfFirmware in
Stage2, OsLoader will assert on APL platform. It was caused by NULL
pointer access in ClearFspHob(). This patch added NULL pointer check
before zeroing out memory. It fixed#197.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Change DEBUG_ERROR to DEBUG_INFO for reporting UpdateFspmSgxConfig() and
UpdateFspsSgxConfig() return statuses since failing to update FSP
variables for Intel(R) SGX is not necessarily due to an error.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
Necessary FSP header files(ex. Fsp*Upd.h) will be copied from FSP
release repo. Additionally, cfl target for WHL/CFL platforms will
verify minimum FSP version like apl target.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL, if using Boot Guard profile 0, booting from BP1 will be
significantly slower than BP0. It is because some code region in BP1
is not covered by MTRR cache settings. This patch adjusted MTRR
settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used.
It fixed#188.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
elCaxper