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[CFL] Enable CFL DMA protection code flow 

This patch added required code flow to prepare to enable DMA
protection for CFL platform. Platform code needs to build a
VTD_INFO structure, and then call SetDmaProtection to enable
and disable DMA protection at different initialization phase.
Platform needs to enable DMA protection as early as possible
after memory is ready. For CFL, VT-d PMR cannot be fully enabled
before FspSiliconInit. So it was postponed to Stage2.

Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Maurice Ma 2020-03-17 21:42:17 -07:00
parent a1df5f9cc5
commit 3af6d70787
8 changed files with 67 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Platform/CoffeelakeBoardPkg/BoardConfig.py
View File

@ -51,6 +51,7 @@ class Board(BaseBoard):
self.HAVE_PSD_TABLE = 1
self.ENABLE_GRUB_CONFIG = 1
self.ENABLE_CSME_UPDATE = 0
self.ENABLE_DMA_PROTECTION = 0
self.DEBUG_PORT_NUMBER = 0xFF
# CSME update library is required to enable this option and will be available as part of CSME kit
@ -157,6 +158,7 @@ class Board(BaseBoard):
'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
'HeciLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciLib/HeciLib.inf',
'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
'VtdPmrLib|Silicon/CommonSocPkg/Library/VtdPmrLib/VtdPmrLib.inf'
]
if self.BUILD_CSME_UPDATE_DRIVER:
dsc_libs['IA32'].append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')

1
Platform/CoffeelakeBoardPkg/Library/Stage1ABoardInitLib/Stage1ABoardInitLib.inf
View File

@ -33,6 +33,7 @@
Silicon/CoffeelakePkg/CoffeelakePkg.dec
Platform/CoffeelakeBoardPkg/CoffeelakeBoardPkg.dec
Platform/CommonBoardPkg/CommonBoardPkg.dec
Silicon/CommonSocPkg/CommonSocPkg.dec
[LibraryClasses]
BaseLib

3
Platform/CoffeelakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -223,6 +223,9 @@ UpdateFspConfig (
DEBUG ((DEBUG_INFO, "FSP-M variables for Intel(R) SGX were NOT updated.\n"));
}
// Enable VT-d
FspmcfgTest->VtdDisable = 0;
Fspmcfg->PlatformDebugConsent = MemCfgData->PlatformDebugConsent;
Fspmcfg->PchTraceHubMode = MemCfgData->PchTraceHubMode;
}

1
Platform/CoffeelakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.inf
View File

@ -32,6 +32,7 @@
Silicon/CommonSocPkg/CommonSocPkg.dec
Platform/CommonBoardPkg/CommonBoardPkg.dec
Platform/CoffeelakeBoardPkg/CoffeelakeBoardPkg.dec
Silicon/CommonSocPkg/CommonSocPkg.dec
[LibraryClasses]
BaseLib

51
Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -62,6 +62,7 @@
#include <Library/SmbiosInitLib.h>
#include <IndustryStandard/SmBios.h>
#include <VerInfo.h>
#include <Library/VtdPmrLib.h>
#include <Library/S3SaveRestoreLib.h>
#include "GpioTables.h"
#include <Library/PchSpiLib.h>
@ -905,6 +906,42 @@ UpdatePayloadId (
SetPayloadId (PayloadId);
}
/**
Build VT-d information to prepare PMR program
**/
STATIC
VOID
BuildVtdInfo (
VOID
)
{
VTD_INFO *VtdInfo;
UINT32 McD0BaseAddress;
UINT32 MchBar;
UINT32 Idx;
UINT32 VtdIdx;
UINT32 Data;
UINT32 RegOff[2] = {R_SA_MCHBAR_VTD1_OFFSET, R_SA_MCHBAR_VTD3_OFFSET};
VtdInfo = &((PLATFORM_DATA *)GetPlatformDataPtr ())->VtdInfo;
McD0BaseAddress = MM_PCI_ADDRESS (SA_MC_BUS, 0, 0, 0);
MchBar = MmioRead32 (McD0BaseAddress + R_SA_MCHBAR) & ~BIT0;
VtdInfo->HostAddressWidth = 39;
VtdIdx = 0;
for (Idx = 0; Idx < ARRAY_SIZE(RegOff); Idx++) {
Data = MmioRead32 (MchBar + RegOff[Idx]) & ~3;
if (Data != 0) {
DEBUG ((DEBUG_INFO, "VT-d Engine %d @ 0x%08X\n", VtdIdx, Data));
VtdInfo->VTdEngineAddress[VtdIdx++] = Data;
ASSERT (VtdIdx <= ARRAY_SIZE(VtdInfo->VTdEngineAddress));
}
}
VtdInfo->VTdEngineCount = VtdIdx;
}
/**
Initialize Board specific things in Stage2 Phase
@ -927,7 +964,7 @@ BoardInit (
UINT32 AddressPort;
UINTN SpiBar0;
UINT32 Length;
VTD_INFO *VtdInfo;
EFI_PEI_GRAPHICS_INFO_HOB *FspGfxHob;
LOADER_GLOBAL_DATA *LdrGlobal;
@ -992,6 +1029,13 @@ BoardInit (
if (FeaturePcdGet (PcdSmbiosEnabled)) {
InitializeSmbiosInfo ();
}
// Enable DMA protection
if (FeaturePcdGet (PcdDmaProtectionEnabled)) {
BuildVtdInfo ();
VtdInfo = &((PLATFORM_DATA *)GetPlatformDataPtr ())->VtdInfo;
SetDmaProtection (VtdInfo, TRUE);
}
break;
case PrePciEnumeration:
break;
@ -1091,6 +1135,11 @@ BoardInit (
break;
case EndOfFirmware:
ClearFspHob ();
if (FeaturePcdGet (PcdDmaProtectionEnabled)) {
// Disable DMA protection
VtdInfo = &((PLATFORM_DATA *)GetPlatformDataPtr ())->VtdInfo;
SetDmaProtection (VtdInfo, FALSE);
}
break;
default:
break;

4
Platform/CoffeelakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.inf
View File

@ -54,6 +54,7 @@
PsdLib
S3SaveRestoreLib
BoardSupportLib
VtdPmrLib
[Guids]
gSmmInformationGuid
@ -84,3 +85,6 @@
gPlatformModuleTokenSpaceGuid.PcdSmbiosTablesBase
gPlatformModuleTokenSpaceGuid.PcdSmbiosEnabled
gPlatformCommonLibTokenSpaceGuid.PcdEmmcHs400SupportEnabled
gPlatformCommonLibTokenSpaceGuid.PcdDmaProtectionEnabled
gPlatformCommonLibTokenSpaceGuid.PcdDmaBufferAlignment
gPlatformCommonLibTokenSpaceGuid.PcdDmaBufferSize

2
Silicon/CoffeelakePkg/Include/PlatformData.h
View File

@ -10,6 +10,7 @@
#include <Library/BootGuardLib.h>
#include <Library/BootloaderCoreLib.h>
#include <Library/VtdPmrLib.h>
typedef struct {
UINT8 PlatformId : 5;
@ -21,6 +22,7 @@ typedef struct {
typedef struct {
BOOT_GUARD_INFO BtGuardInfo;
VTD_INFO VtdInfo;
} PLATFORM_DATA;
#endif /* __PLATFORM_DATA_H__ */

4
Silicon/CoffeelakePkg/Include/Register/SaRegs.h
View File

@ -29,8 +29,12 @@
#define SA_MC_FUN 0x00
#define V_SA_MC_VID 0x8086
#define R_SA_MC_DEVICE_ID 0x02
#define R_SA_MCHBAR 0x48
#define R_SA_MC_CAPID0_B 0xE8
#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 // HW UNIT1 for IGD
#define R_SA_MCHBAR_VTD3_OFFSET 0x5410 // HW UNIT3 for all other - PEG, USB, SATA etc
#define CPUID_VERSION_INFO 0x01
#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0