Silicon init with eMMC HS400 mode config (#407)

This patch is a follow-up patch of #380. If a platform disables HS400 mode,
silicon init code will configure eMMC in HS200. Other modes not in scope.

This will also fix #406.

Signed-off-by: Aiden Park <aiden.park@intel.com>
This commit is contained in:
Aiden Park 2019-10-21 09:30:51 -07:00 committed by GitHub
parent 2b753e922b
commit 33e18bc1bc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 7 additions and 2 deletions

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@ -1019,6 +1019,9 @@ UpdateFspConfig (
FspsConfig->SdioEnabled = (UINT8)DevEnCfgData->DevEnControl1.SdioEnable;
FspsConfig->SmbusEnable = (UINT8)DevEnCfgData->DevEnControl1.SmbusEnable;
// Set HS200 if HS400 is disabled. No DDR50 in scope.
FspsConfig->eMMCHostMaxSpeed = (UINT8)((FeaturePcdGet (PcdEmmcHs400SupportEnabled) != 0) ? 0 : 1);
FspsConfig->PortUsb20Enable[0] = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port0Enable;
FspsConfig->PortUsb20Enable[1] = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port1Enable;
FspsConfig->PortUsb20Enable[2] = (UINT8)DevEnCfgData->DevEnControl2.Usb20Port2Enable;

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@ -98,3 +98,4 @@
gPlatformModuleTokenSpaceGuid.PcdSmramTsegBase
gPlatformModuleTokenSpaceGuid.PcdSmramTsegSize
gPlatformModuleTokenSpaceGuid.PcdFuncCpuInitHook
gPlatformCommonLibTokenSpaceGuid.PcdEmmcHs400SupportEnabled

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@ -1327,7 +1327,7 @@ UpdateFspConfig (
FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 = 0;
FspsUpd->FspsConfig.ScsEmmcEnabled = 1;
FspsUpd->FspsConfig.ScsEmmcHs400Enabled = 1;
FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)((FeaturePcdGet (PcdEmmcHs400SupportEnabled) != 0) ? 1 : 0);
FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
FspsUpd->FspsConfig.ScsUfsEnabled = 0;

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@ -80,4 +80,5 @@
gPlatformModuleTokenSpaceGuid.PcdSmbiosStringsPtr
gPlatformModuleTokenSpaceGuid.PcdSmbiosStringsCnt
gPlatformModuleTokenSpaceGuid.PcdSmbiosTablesBase
gPlatformModuleTokenSpaceGuid.PcdSmbiosEnabled
gPlatformModuleTokenSpaceGuid.PcdSmbiosEnabled
gPlatformCommonLibTokenSpaceGuid.PcdEmmcHs400SupportEnabled