On TGL, Linux reported ACPI errors on missing PRES method for SATA
port 0. This patch added the missing PRES implementation for all
SATA ports.
This fixed#1497.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL ACPI table does not define any I2C pad or panel. And
it will cause ACPI error for Linux. This patch added conditional
scope for I2C pad and panel reference so that if pad type or panel
type is not defined, these scope will not be used by ACPI.
This fixed#1496.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Fix two errors:
ACPI Error: Aborting method \_SB.PR00.GCAP due to previous error
(AE_INVALID_TABLE_LENGTH)
ACPI Error: Aborting method \_SB.PR00._PDC due to previous error
(AE_INVALID_TABLE_LENGTH)
UEFI BIOS always does dynamic loading, but SBL does static loading
instead.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Pass in a pch_series param to GpioDataConvert tool
to fetch the correct gpio group info for a platform
based on the pch series.
The tool expects the platform specific config file to
implement a function vir_to_phy_grp () that returns
a BOOL value based on:
If vir_to_phy_grp = False, SBL's config has A->0, B->1 etc. mapping.
And GpioSiLib.c or GpioInitLib.c corresponding libraries will map
this virtual group #s to real physical group #s (if not same).
If vir_to_phy_grp = True, SBL's config has A->G1, B->G2 etc.
physical mapping directly, so the GpioLib library uses this as is.
GpioDataConfig.py file was added for ADL platform.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Current TGL platform set 0 as the PCI end bus number in ACPI
MCFG table. And it caused incorrect MMCONFIG range calculation in
Linux. This patch updated the template to use 0xFF as the PCI
end bus number.
It should fix#1481, to be confirmed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When run as part of an automated system it's important to ensure that
any failure is reported to the calling process. Writing an error message
and then exiting indicating success leads to difficult-to-diagnose
problems.
Signed-off-by: Mike Crowe <mac@mcrowe.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-s.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for TGL.
Verified: TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
s0ix feature enabling flag also turn off some FSP configs
so that default SBL image can't detect the onboard Lan
and type c devices.
Signed-off-by: Randy Lin <randy.lin@intel.com>
This patch fixes no activity on UART0 pins when enabling it for serial
communication.
In TGL, there are two UART0 instances (GPP_C8~C11 and GPP_F0~F4) while
one (GPP_F0~F4) is shared with CNVI. This patch enables GPP_C8~C11 as
the UART0 instance to reduce the conflict with CNVI.
This patch also fixes the GPIO pins definition for TGL-H and moves
serial io initialization code to SerialIo.c to simplfy Stage2BoardInitLib.c.
Test: TGL-UP3 RVP and TGL-H RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
IsMarkedBadDso and InvalidateBadDso would be required for all
the platforms that support TCC. And the implementation is also
common, so just move them to common TccLib.
Also updated the implementation to remove SPI flash erase for
InvalidateBadDso().
Signed-off-by: Guo Dong <guo.dong@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch invalidates the DSO region with a marker after
a DSO hang (caused by corrupted DSO) is detected (by WDT timeout).
With the marker, stage1b can know the DSO tuning should be skipped.
The bad DSO mark is defined as both Signature and Size in the
TCCT component header are zero.
With this patch, the previous defined WDT scratchpad bit,
WDT_FLAG_TCC_BAD_DSO, is removed.
TEST=Verified on TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch solves an infinite reset loop issue caused
by bad DSO with the scenario:
After platform reset (due to WDT timeout), FSPm asks
for another reset, but before that, WDT_FLAG_TCC_DSO_IN_PROGRESS
is already cleaned. As a result, in the thrid reset, stage1B
will have no idea about the DSO is corrupted and it
continues boot with Tcc Tuning flow, which causes WDT
timeout reset again.
This patch introduces a WDT_FLAG_TCC_BAD_DSO flag in WDT
scrachpad (bit 18). The flag is a marker that is set when
a bad DSO is detected. The new booting flow for "bad DSO" case
if Tcc_Tuning enabled will be:
1st boot: (after fwupdate)
- TCC_DSO and WDT set by stage1b and stage2
- FSP hangs and trigger WDT reset
2nd boot:
- Stage1b detects "bad DSO" because of WDT and
TCC_DSO_IN_PROGRESS. For this case:
Clear TCC_DSO_IN_PROGRESS and WDT.
Set TCC_BAD_DSO.
Then it continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
- FSPm asks for a reset
3rd boot:
- Stage1b detects "bad DSO" because of TCC_BAD_DSO
It continues boot that will skip Tcc Tuning
(because of TCC_DSO_IN_PROGRESS unset)
The patch does not remove the 200-sec abnormal boot-up symptom
because the symptom is noticeable to user. So user can be aware
of something wrong (bad DSO).
The "bad DSO" flag will be clear before fwupdate, so a fwupdate
with a correct DSO can solve the 200 sec abnormal boot up time.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Config 1/3 RVP boards can't share same IFWI image
and it is required to adjust the FIT parameters.
Add -o cfg3 to support this.
Signed-off-by: Randy Lin <randy.lin@intel.com>
GPIO payload selection settings can be made
into a platform optional common config. This
will ensure that the options display the same
across all platforms which add support for
the GPIO payload selection feature. Each
platform will need to include the
CfgData_PayloadSelection.yaml and needs to
create their own CfgData_GpioPadGroups.yaml
to provide the list of GPIO pad groups to
select from.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch does the following updates to SmBiosInitLib:
1. Provide AddSmbiosType() to add a SmBios Type header.
2. Provide AddSmbiosString() to append strings to Type header.
3. Move Finalize() to after 'PrePayloadLoading' board init phase.
All Smbios related calls need to be done before this.
4. Modified TGL project to adjust to these changes.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
When multiple USB devices are attached, current SBL will try to
boot the device with index specified by HwPart in the boot option.
However, it is hard to determine the USB device index order since
it depends on which port the device is connected to. Instead, for
USB devices, SBL can try to boot from each of them until the boot
image is loaded successfully or all USB devices have been tried out.
This patch added this support.
To enable this feature, it is required to set the USB boot option
HwPart to 0xFF.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
In order to improve the UEFI payload display performance, it is
desirable to have the framebuffer as write-combining for cache
attribute. This patch added a common API to enable this and it
enabled the GFX framebuffer cache for QEMU and TGL. Other
platforms still need porting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The patch updates CfgData yaml to align with FSP:
1. correct value range for SaGv
2. remove unused variables: FreqSaGvLow and FreqSaGvMid
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Current GpioLib uses 2 bits from OtherSettings to
configure RxRaw field in GPIO PAD CFG DWORD 0. But
Gpio config templates are missing the option to configure
this feature. This patch adds the option in template.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
Current SBL uses DLT file to override the GPIO group id in the
GPIO CFGDATA table because the group ID used in CFGDATA needs to
match the group ID used by GPIO library. This patch decoupled the
GPIO group id with the GPIO library. Instead, a translation was
added to convert the group ID to the value required by the GPIO
library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When some settings from DSO caused system hang, the WDT
would cause the system reboot. And in the next boot,
SBL would use the default setting by not apply the DSO
values.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added PcdAcpiProcessorIdBase to allow platform to
customize the processor ID start base within MADT APIC entry.
Current EHL and TGL declared PR00 processor object in ACPI
with unique ID value 0, but other projects used vlaue 1
instead. This patch will help fix this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled several config options for TGL x64 build so that
64 bit PCI resource can be allocated properly. As part of it, the
related GFX bar read/write has been extended to handle 64bit address.
This has been tested on UPX i11 board. X64 SBL can boot to Ubuntu
properly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixes three S0ix issues:
1. a regression caused by commit 20889 where the
FspsConfig->SerialIoUartMode missed configuring for legacy UART
2. failed s0ix when assigning uart port2 as debug port: root caused
by Maurice. He pointed out that several uart properties should
not be reset
This fixed#1314.
3. conflict with TCC/TSN: In TGL, S0ix should be disabled when either
TCC or TSN is enabled. If s0ix is enabled, the patch checks TCC/TSN
enabling status and forces turning off S0ix if TCC/TSN is enabled.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
By default, the boot option 0 has mender OS boot flag set, and it causes
"root=" to be appended to the Linux boot command line. For Ubuntu OS,
it will cause the wrong root fs parameter and prevent it from booting.
This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added PCI MEM64 resource in ACPI table so that OS can
re-allocate 64bit PCI resource if required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
On TGL warm reset flow, current MRC will always do full MRC training.
It is because of wrong PMC rigster was used in platform code to set
and clear the MRC scratch pad bit.
This fixed#1346.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Ubuntu 20.04.3 can support TGL platform. However, current SBL won't
be able to boot without changes. It is caused by following issues:
- GRUB CFG support is not enabled by default
- Payload heap is too small to load the full INITRD image
- USB boot option is set to boot from partition 1 and EXT2 filesystem.
This patch addressed above issues. It has been tested on UPX i11.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed the USB enumeration long delay issue seen on
UPX i11 board. It disabled the malfunction USB port 8.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In the TGL implementation of UpdateFspConfig() in Stage1BBoardInitLib.c,
there are two missing UPD updates that have been validated for TGLH. This
manifested itself when enabling the TCC feature by setting ENABLE_TCC in
BoardConfig.py by reporting a bad VT-d descriptor and hanging.
This patch incorporates these two UPD settings for the TGLH boards.
Signed-off-by: Jim A. Pelner <jim.pelner@intel.com>
On TGL UpdateFspConfig() funciton in Stage2BoardInitLib.c has code
path to return early, it will skip all remaining UPD initialization.
The code should always continue the flow to finish the whole
function. This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
1. HD Audio and TSN share pins. These are mutually exclusive features.
2. RVP board should be reworked to support legacy HD Audio mode.
Signed-off-by: Randy Lin <randy.lin@intel.com>
- UP3 IoT FSP MR3
- change the FSP headers from FspBin folder to Include folder
- update TGL platform version to 1.3
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch added payload selection GPIO configuration and removed
hardcoded GPIO pin for payload selection.
It also fixed#1195.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are too many pins in GPIO pin configurations in TGL platform.
It is desired to group them into sub-pages to make it easy to find
the proper pin for configurations. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For the UPX i11 board we need to set
the SA display table (same as DDR4 RVP),
populate the VBT callback routine (also
same DDR4 RVP), and update the SMBIOS
base board string.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Need to adjust the CFG data settings
related to PCIe to enable several
devices for the UP Xtreme i11 board.
Able to detect M.2 NVMe, x4 PCIe slot,
and network controller 8086-0D9F.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
With the recent additions to the CFG data (new DLT for
UPXi11 and new fields added) the CFG data size alloced
in memory seems to have run out of space, need to add
space to load the CFG data. Also, we need to specify
in FSP-M to skip UART init for the debug port we are
using when it is a PCH UART or we lose debug messages
in Stage2 onward if using a debug FSP.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
The default values for USB20Enable from FSP
is set to enabled. Some platforms need to
disable some of these USB20 ports (e.g. TGL-U
DDR4 and LPDDR4 RVP). Add CFG data field for
the USB20Enable settings per port.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Maurice Ma