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[TGL] Increase CFG data mempool and skip debug UART init 

With the recent additions to the CFG data (new DLT for
UPXi11 and new fields added) the CFG data size alloced
in memory seems to have run out of space, need to add
space to load the CFG data. Also, we need to specify
in FSP-M to skip UART init for the debug port we are
using when it is a PCH UART or we lose debug messages
in Stage2 onward if using a debug FSP.

Signed-off-by: James Gutbub <james.gutbub@intel.com>
This commit is contained in:
James Gutbub 2021-09-16 11:35:07 -07:00 committed by Guo Dong
parent 6e3da33852
commit de3b09f331
2 changed files with 2 additions and 1 deletions
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2
Platform/TigerlakeBoardPkg/BoardConfig.py
View File

@ -206,7 +206,7 @@ class Board(BaseBoard):
self.LOADER_RSVD_MEM_SIZE = 0x500000
self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE + 0x1000
self._generated_cfg_file_prefix = 'Autogen_'
# _CFGDATA_INT_FILE - Internal cfg data is generally used for internal boards like MRBs, RVPs etc.

1
Platform/TigerlakeBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
View File

@ -188,6 +188,7 @@ UpdateFspConfig (
if (DebugPort < PCH_MAX_SERIALIO_UART_CONTROLLERS) {
Fspmcfg->PcdDebugInterfaceFlags = BIT4;
Fspmcfg->SerialIoUartDebugControllerNumber = DebugPort;
Fspmcfg->SerialIoUartDebugMode = 4;
} else {
Fspmcfg->PcdDebugInterfaceFlags = BIT1;
if (DebugPort == 0xFF) {