Ubuntu 20.04.3 can support TGL platform. However, current SBL won't
be able to boot without changes. It is caused by following issues:
- GRUB CFG support is not enabled by default
- Payload heap is too small to load the full INITRD image
- USB boot option is set to boot from partition 1 and EXT2 filesystem.
This patch addressed above issues. It has been tested on UPX i11.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed the USB enumeration long delay issue seen on
UPX i11 board. It disabled the malfunction USB port 8.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Since the commit below was reverted
24f5aa59b5. The cache flush
need to be moved into the place where data consistency
across warm reset is required. The patch added the WBINVD
to flush the cache before "fwupdate" command issues warm
reset.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On UPX, one USB2 port does not respond properly during PCI enumeration.
It needs to be disabled. The current SBL code disabled the wrong port.
It should be port 10 (USB2 index 9).
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In the TGL implementation of UpdateFspConfig() in Stage1BBoardInitLib.c,
there are two missing UPD updates that have been validated for TGLH. This
manifested itself when enabling the TCC feature by setting ENABLE_TCC in
BoardConfig.py by reporting a bad VT-d descriptor and hanging.
This patch incorporates these two UPD settings for the TGLH boards.
Signed-off-by: Jim A. Pelner <jim.pelner@intel.com>
During UP Extreme board enabling, trace hub interface was enabled
to help debug. But it should be disabled by default. This patch
fixed it.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On TGL UpdateFspConfig() funciton in Stage2BoardInitLib.c has code
path to return early, it will skip all remaining UPD initialization.
The code should always continue the flow to finish the whole
function. This patch fixed this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
1. HD Audio and TSN share pins. These are mutually exclusive features.
2. RVP board should be reworked to support legacy HD Audio mode.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Seems some recent patches may have added additional
size to OS Loader and now the internal pre-commit build
test in Jenkins is failing due to not enough space
for PAYLOAD. Other platforms are also using 29000h
so might be best to increase the CFL value as well.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Current SBL code uses MSR(0xce) to calculate the CPU TSC frequency.
However, it is not very accurate. A better way is to use CPUID to
calculate the TSC frequency. This patch added new API to get accurate
TSC frequency. It also added APIs to allow conversion between time
and TSC ticks.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL build will show lots of FSP files as untracked files.
This patch re-orgnized the rules for .gitignore file so that it
has better control at different folder level. With these new rules
no untracked files will be shown for the FSP and VBT files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On SBL, it can support boot option selection through QEMU command line
"-boot order" parameter. However, it does not work anymore. It was
because of the MAX_BOOT_OPTION_CFGDATA_ENTRY adjustment in other commit.
This patch decoupled internal boot option index with the CFGDATA boot
option index so that it does not have impacts on each other. With this
change, QEMU boot option can be altered through command line again.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The newly added code caused build issue for EHL and CMLv x64 due to
insuffiant flash space. This patch adjusted the flash layout to fix
the build failure.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch clears RTC alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
In addition to clearing RTC SMI#, this patch also clears other
SMI# as UEFI BIOS does.
Test method: rtcwake -m -s 15
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- UP3 IoT FSP MR3
- change the FSP headers from FspBin folder to Include folder
- update TGL platform version to 1.3
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Disable the new GPIO scheme by default in dlt file
Only enable this option for kernel version 4.18.0-315
Alternatively with kernel module parameter
'module_blacklist=pinctrl_elkhartlake' will works
without enabling this GPIO scheme.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Currently the PLT_DEVICE_TABLE is limited
to only using OS_BOOT_MEDIUM_TYPE devices
but ideally should be capable of mapping
any system device into the table. For the
time being we will remove the OsBootDeviceGraphics
since it created some KW issue in the fs command.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
On QEMU or Smimics, it might need to do native GFX initialization
if the GFX is not initialized by FSP. This patch added the native
GFX support for BOCHS graphics controller.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch upstreams previous CML patch for RC3 hotfix:
[CMLV] Fix chipsec SMM issues in S3 path:
Trigger SMI in S3 path to let UEFI payload restore registers.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added payload selection GPIO configuration
hardcoded GPIO pin for payload selection.
It also fixed#1196.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Co-authored-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added payload selection GPIO configuration and removed
hardcoded GPIO pin for payload selection.
It also fixed#1195.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are too many pins in GPIO pin configurations in TGL platform.
It is desired to group them into sub-pages to make it easy to find
the proper pin for configurations. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For the UPX i11 board we need to set
the SA display table (same as DDR4 RVP),
populate the VBT callback routine (also
same DDR4 RVP), and update the SMBIOS
base board string.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Need to adjust the CFG data settings
related to PCIe to enable several
devices for the UP Xtreme i11 board.
Able to detect M.2 NVMe, x4 PCIe slot,
and network controller 8086-0D9F.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
With the recent additions to the CFG data (new DLT for
UPXi11 and new fields added) the CFG data size alloced
in memory seems to have run out of space, need to add
space to load the CFG data. Also, we need to specify
in FSP-M to skip UART init for the debug port we are
using when it is a PCH UART or we lose debug messages
in Stage2 onward if using a debug FSP.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
The default values for USB20Enable from FSP
is set to enabled. Some platforms need to
disable some of these USB20 ports (e.g. TGL-U
DDR4 and LPDDR4 RVP). Add CFG data field for
the USB20Enable settings per port.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
The GPIO for the UP Xtreme i11 board
needs to be synced by obtaining the
GPIO diff between the default BIOS on
the board and the default GPIO programming
being performed currently by SBL.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
There are several config options that will be overridden in Stage
code when S0ix is enabled and so we should hide these in the
ConfigEditor if S0ix is enabled.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- enable s0ix by default for TGL-U
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This patch fixes a hang issue during fw update caused by
mismatching bios rom size. For a fw update, the TopSwap
size, Redundant Region size, and total BIOS region must be
identical.
This patch also adds check on rom size during fw update.
The check only works for a running SBL built with this patch.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
There is a discrepancy between how Linux reads GPIO
and how bootloader is presenting it. This causes Linux
distros to crash, even in the installer,unless a kernel
module parameter has been passed:
'module_blacklist=pinctrl_elkhartlake'
The customer, Red Hat, is using RHEL 8 4.18.0-315.
There appears to be a discrepancy between how Linux reads GPIO and how
the Intel BIOS is presenting it.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Support for Up Xtreme i11 TGL based board has
been started, with this patch we are able to
boot the board using Slim Bootloader via OS
Loader payload. The PCIe x4 slot on the board
is able to detect NVMe-to-PCIe x4 adapter media
but the other IO on the Up Xtreme i11 board
will need enabling in subsequent patches. Debug
output is coming from header CN11 on the board
(e.g. UART2).
To stitch the SlimBootloader.bin into the default
IFWI retrieved from the Up Xterme i11 use the
StitchLoader.py script with '-p' argument as given
below:
python Platform\TigerlakeBoardPkg\Script\StitchLoader.py -p 0xAA000204
-i board_default_ifwi_orig.bin -s Outputs\tgl\SlimBootloader.bin
-o sbl_ifwi_tgl-upx.bin
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Not every board will want to boot with
Fusa Enabled (ex. UPX i11 board). We can
allow for Fusa to be skipped using CFG
instead of just BoardConfig flag.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
When boot guard profile is non-zero the OemPublicKeyHash
will be populated in the stitching XML file but FIT/mFIT
is giving a warning message:
OemPublicKeyHash. Exception: set_value failed.
This will remove the trailing space added to the last byte
given in the OemPublicKeyHash and resolve the warning.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
The patch enables stitching CML/CMLV IFWI under Linux.
CML/CMLV stitch tools do not natively support for Linux.
A wrapper using 'wine' is required and works.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch fixes TSeg region full problem after multiple
warn reset. Each time of warm reset, except S3 resume, the
TSeg region should be clear.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Use PchHdaEnable in cfgdata for user to configure the desire value.
TEST=Verified audio function on tglu platform
Signed-off-by: Randy Lin <randy.lin@intel.com>
For EHL, PCH & PSE TSNs are required to be turned on for ethernet
connection. However, TSN configurations binaries (TSN Mac address,
TSN manual config & PSE TSN IP config binaries) are optional, and
only used for refined controls.
This CL decouples optional TSN binaries loading and can be enabled
with BoardConfig flag "ENABLE_TSN". If those binaries are
not included, OS TSN driver will load TSNs with default configs and
assign MAC address to them dynamically.
ENABLE_TSN is turned off by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
EHL stitchifwi script enables user to replace IFWI IPFW components
during stitching time.
This CL enables user to only replace IPFW component only if the
specific component is included in IPFW folder of stitch workspace
directory.
Besides, this CL also adds TCC CRL to the replaceable IFWI IPFW
components list.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Here are the changes:
1. Update mismatched & incorrect config options & variables
2. Fix invalid boot options configs
3. [common] Include 'preOS + mender' support for boot flags in
boot options template
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
According to EDS, TCSS PTM Enable (PTME on [B0,D7,F0] offset 158h)
should not be set unless a associated downstream port already has
PTM Enable set.
This patch adds a CfgData control for each TCSS PCIe Root Port.
User can enable each of them when a downstream port meets the
requirement. The new CfgData control is similiar to the following
setup in UEFI BIOS Menu:
Intel Advanced -> SA -> TCSS -> PCIE RP[]
Last, this patch also removes redundant PTM configurations,
because (a) this PTM settings will be overridden by built-in
CfgData_Silicon.yaml or customized DLT; b) even for customized SBL,
FSP can use default PTM settings.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Allow user to include TCC CRL binary to be included in SBL
binary build. The script will check if crl.bin is there (binary
folder) and then only include it.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This patch refactors TSN enablement control by
- rename ENABLE_TSN_MAC_ADDRESS with ENABLE_TSN:
align the naming with ENABLE_TCC
- ENABLE_TSN can be used as a one-stop control knob
to reserve FW spaces and include proper TSN CfgData
- collect TSN-specific CfgData into CfgData_Tsn_Feature.dlt
With the new control, inconsistent TSN settings are fixed:
- TSN MAC FW space is reserved but PchTsnEnable is not set
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Recently, github CI test case, Qemu-linux_boot.py, randomly fails.
Comparing the logs between failed and pass cases, we can find:
1. the failure is caused by timeout before Minimal Linux
completely boots into console and shows "Welcome to Minimal
Linux" messages.
Although such timeout can be a real error (true-positive),
it is also possible just a false alarm (false-positive)...
2. for a failed case, a force push to trigger another CI check
can result in pass, even no code changes. Thus, the timeout
failure points to CI environment (e.g., loading) - a false alarm.
3. the margin (of pass case to timeout) is about 0.4 sec.
This patch increases timeout for 2 seconds to avoid unexpected
test timeout caused CI envornment (e.g., loading).
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Default Bpmgen params created by bpmgen tool
has unicode characters. This patch fixes reading the
file with unicode chars.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
when pin number in pad name is not in <group name><xx> where
xx is pin number format. for example GPIO_VER2_LP_GPP_C2 instead of
GPIO_VER2_LP_GPP_C02, current code has a bug which does not give the
desired output which is GPP_C02.
This patch fixed this issue.
TEST= Verified on multiple platforms that the issue is fixed
Signed-off-by: Raghava <raghava.gudla@intel.com>
This patch clears RTC Alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
This patch also refactors RegRead/RegWrite in RestoreS3RegInfo
to avoid the misalingment of function pointers and coding
convention.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
TSN GBE PMECTRLSTATUS register returned 0x3 after
booting into OS and only occured in Fusa sku
This fix will check TSN PMECTRLSTATUS register and
update value to 0x0 if non-zero value was returned
Only applicable if TSN is enabled
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
CPOC is defined in both Cpu0Hwp.asl and Dsdt/Cpu.asl,
which results in Linux kernel warning and wrong CPU
base speed shown in Windows 10.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
To support rtcm image for all boot options in SBL EHL
Uncomment boot flags and image type in Tcc_Feature.dlt for
enabling tcc in dedicated boot option
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Current index only support up to 0xF as the CFGHDR_TMPL
as it amend into 0x05 (eg. 0x05$(1))
Update the logic to (0x050 + $(1)) instead to support
index larger than 0xF
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch replaces the original hard-coded iTBT
root ports enabling control with a CFG option.
The default value is to enable them.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Enable DAM option in stitchifwi script for
ITP/CCA debug purpose with -o debug paramter
Example: To enable SATA and DAM enabled "-o sata;debug"
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Update EHL BoardPkg version to 2.0 to allign with current
software package version:
PROJ_MAJOR_VER -> 2 (Maintenance Release candidate)
PROJ_MINOR_VER -> 0 (1st revision of MR1 release)
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Re-enable sbl_rtcm in EHL boot option due to
mistakenly removed it in previous commit of
f01a5b33fb
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch provides exampole on how to enable mailbox debug port on
WHL. To enable it, the following needs to be set in BoardConfig.py.
self.DEBUG_OUTPUT_DEVICE_MASK = 0x07
self.CONSOLE_IN_DEVICE_MASK = 0x00000005
self.CONSOLE_OUT_DEVICE_MASK = 0x00000005
Also adjust the PcdMailboxDebugPortMmioBase value in BoardConfig.py
as needed.
On host side, python script can be used in ISD to read/write this
register using IPC interfaces. EX:
import ipccli
ipc = ipccli.baseaccess()
ipc.stateport.cnp_tpsb0.tap2iosfsb32 (...)
Please refere to MailboxDebugPort.py for example.
This was tested on UPX board with CCA debuger connected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows to use a mailbox register (DWORD) to support debug
port. If CCA debug is connected, it is possible to access certain
SOC register through BSSB. Then this register can be used for debug
console input/output.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds DebugPortLib as a platform extention lib to add new
debug port support. It also adds a generic GpioDebugPortLib to allow
GPIO bit bang to emulate UART TX pin.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Enable POSC for all boot medium in Cfgdata_BootOption.yaml
by default
If Non-Fusa sku was detect and the boot flag will
change to exclude POSC
User can modify the boot flag to exclude the POSC in
yaml file as well
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Add latest Intel® Time Coordinated Computing support for EHL.
Here are the changes:
- Update the TCC subregion layout
- Use the common TCC config data
- Use the common TCC library for RTCT table
- Support TCC DSO cfg, Cache cfg and CRL binaries loading
- Rename TCC variable to follow TCC V2 naming
- Increase the stage 2 size from 0x89000 to 0x91000 to accommodate
the new changes
- Add latest FspmUpd and FspsUpd header files for TCC v2 support
(will be removed once FSP github updated the latest EHL FSP package)
- Change default boot options for RTCM support
TCC mode is turned off by default.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
Fix mPchSciSupported flag checking before changing the
flag value of boot option.
This bug was introduced from commit
b78cbcf128
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Fixed issue #1197
Check PlatformID before proceed to detect from SMBus
Moved PlatformIdInitialize to PostConfigInit
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
- Add knob for setting up the ISI configuration file (isi_conf)
- Fix PT test mask value to be aligned with default PT binary
capabilities. Only add mask when PT is enabled.
- "pt" parameter always requires isi_conf file. Dependency added
automatically. isi_conf is also externally configurable since can
be used without PT.
Signed-off-by: Pedro Queiros <pedro.queiros@intel.com>
Add a separate cfgdata dlt file to enable TCC config data.
The TCC dlt file will be appended to board dlt file when
ENABLE_TCC is set in BoardConfig.py.
Removed RTCM subregion and update boot option for RTCM support
TCC is disabled by default.
Signed-off-by: Guo Dong <guo.dong@intel.com>
MR2 FSP is available so update SBL to use MR2 FSP.
and also use new Microcode required by new FSP
Update platform code on FSP UPDs, especially enable TCC feature.
Update TGL platform version to 1.2 since MR2 released.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Update EHL BoardPkg version to 1.1 to allign with current
software package version:
PROJ_MAJOR_VER -> 1 (Production Release candidate)
PROJ_MINOR_VER -> 1 (2nd revision of PV release)
Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
Remove TGL-H GPIO definition and program.
Use R_ACPI_IO_SMI_STS instead of "R_ACPI_IO_SMI_EN + 4"
Set PCIE region len to 0x10000000 instead of 0x20000000
Remove data dumping for PSD
Fix other typo
Signed-off-by: Guo Dong <guo.dong@intel.com>
Change BiProcHot value to 0 for Fusa sku as per
requested from PMC team to fulfill Fusa requirement
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
When PCH UART is used as debug UART, the later stage code should
not do re-initializaiton. This patch will skip PCH UART GPIO
reprogramming and FSP-S UART re-initialization.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
On TGL platform, if change current DEBUG UART to PCH UART, there
is no output from SBL at all.
This patch fixed this issue by:
- Skip UART init in FSP-T and let SBL do UART init itself.
- Disable any debug output before UART init is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
If the PlatformId is already set by stitch data, the platform code
should skip platform settings to avoid PlatformID override.
This patch adds the PlatformId check in platform code.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Maurice Ma