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[TGL] Add iTBT PCIe root port enablement config (#1217) 

This patch replaces the original hard-coded iTBT
root ports enabling control with a CFG option.
The default value is to enable them.

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This commit is contained in:
stanley 2021-07-08 00:06:54 +08:00 committed by GitHub
parent de2761170e
commit 2832972ad6
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 8 additions and 4 deletions
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7
Platform/TigerlakeBoardPkg/CfgData/CfgData_Silicon.yaml
View File

@ -169,6 +169,13 @@
Enable(Default)- Enable IGFX RenderStandby, Disable- Disable IGFX RenderStandby
length : 0x01
value : 0x1
- ITbtPcieRootPortEn :
name : Enable/Disable ITBT Root Port
type : EditNum, HEX, (0x00,0xFFFFFFFF)
help : >
Enable/Disable ITBT Root Port
length : 0x04
value : { 0x1, 0x1, 0x1, 0x1 }
- PmSupport :
name : Enable/Disable IGFX PmSupport
type : Combo

5
Platform/TigerlakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c
View File

@ -1588,15 +1588,12 @@ UpdateFspConfig (
FspsConfig->SkipMpInit = 0;
FspsConfig->UsbTcPortEn = 0xf;
FspsConfig->ITbtPcieRootPortEn[0] = 0x1;
FspsConfig->ITbtPcieRootPortEn[1] = 0x1;
FspsConfig->ITbtPcieRootPortEn[2] = 0x1;
FspsConfig->ITbtPcieRootPortEn[3] = 0x1;
if (SiCfgData != NULL) {
FspsConfig->EnableTimedGpio0 = SiCfgData->EnableTimedGpio0;
FspsConfig->EnableTimedGpio1 = SiCfgData->EnableTimedGpio1;
FspsConfig->XdciEnable = SiCfgData->XdciEnable;
CopyMem (FspsConfig->ITbtPcieRootPortEn, SiCfgData->ITbtPcieRootPortEn, sizeof(SiCfgData->ITbtPcieRootPortEn));
}
if (FeaturePcdGet (PcdTccEnabled)) {