* fix: [Common] FwVendor/OemId Array compared against 0
Since it is an array the test evaluates as true and the check is
unnecessary.(CWE-398)
UINT8 FwVendor[EFI_ACPI_PSD_FW_VENDOR_SIZE];
UINT8 OemId[6];
Signed-off-by: Randy <randy.lin@intel.com>
* fix: [Common] Unchecked return value for HeciGetMeMode
If the function returns an error value, the error value
may be mistaken for a normal value.
In HeciSend: Value returned from a function is
not checked for errors before being used. (CWE-252)
Signed-off-by: Randy <randy.lin@intel.com>
---------
Signed-off-by: Randy <randy.lin@intel.com>
- update FSP version to IoT FSP 5505_01_MR7 (0A.00.7D.72)
- update TGLU microcode version to A6
- update TGLH microcode version to 42
- update TGL platform version to 1.7
Signed-off-by: Vincent <vincent.chen@intel.com>
- update FSP version to IoT FSP 5143_01_MR6 (0A.00.7B.31)
- update VBT version to IoT FSP 5143_01_MR6 (250)
- update TGLU microcode version to A4
- update TGL platform version to 1.6
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
The patch enables PCIe PM features by,
1. Store Root Port configuration before FSP-s.
2. Configure Pcie RP in PostPciEnumeration with the stored RP config.
The feature is controlled by ENABLE_PCIE_PM and the corresponding
PcdEnablePciePm
The implementation is silicon-dependent, because of registers definition.
The PciePmNull component is a generic implementation. This patch also
implements PciePm for TGL.
Verified: TGL-U RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- update FSP/VBT version to UP3 IoT FSP MR4
- update TGLU microcode version to 9A
- update TGL platform version to 1.4
- remove redundant files in case of files not being updated
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch added additional files to be excluded from patch check.
For example, txt, ini, app, common, template, rule, Makefile,
GNUmakefile, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
- UP3 IoT FSP MR3
- change the FSP headers from FspBin folder to Include folder
- update TGL platform version to 1.3
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- enable s0ix by default for TGL-U
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This patch fixes a hang issue during fw update caused by
mismatching bios rom size. For a fw update, the TopSwap
size, Redundant Region size, and total BIOS region must be
identical.
This patch also adds check on rom size during fw update.
The check only works for a running SBL built with this patch.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
The patch adds a feature to read Dts at boot. The feature
is analogous to UEFI BIOS:
Thermal Conf -> Platform Thermal Conf -> Boot DTS Read
Specifically, the feature reads Tjunctions of PCH and CPU
and stores them as Smbios Type-28 entries.
The patch also fixes AppendSmbiosType in SmbiosInitLib:
A newly added structure should inherit the Handle from
previous Type-127 (end-of-table) structure.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
MR2 FSP is available so update SBL to use MR2 FSP.
and also use new Microcode required by new FSP
Update platform code on FSP UPDs, especially enable TCC feature.
Update TGL platform version to 1.2 since MR2 released.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Remove TGL-H GPIO definition and program.
Use R_ACPI_IO_SMI_STS instead of "R_ACPI_IO_SMI_EN + 4"
Set PCIE region len to 0x10000000 instead of 0x20000000
Remove data dumping for PSD
Fix other typo
Signed-off-by: Guo Dong <guo.dong@intel.com>
On TGL platform, if change current DEBUG UART to PCH UART, there
is no output from SBL at all.
This patch fixed this issue by:
- Skip UART init in FSP-T and let SBL do UART init itself.
- Disable any debug output before UART init is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Updated ACPI Tables, NVS data and FSP UPDs for S0ix support
S0ix is working on yocto through USB boot and windows through CPU M.2 NVME
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Update the TCC subregion layout.
Use the common TCC config data
Use the common TCC library for RTCT table.
Rename TCC variable to follow TCC V2 naming
Pending the FSP release for TCC V2 support.
Signed-off-by: Guo Dong <guo.dong@intel.com>
TGL supports multiple OEM keys and their revocation
by CSE. This patch supports HECI APIs for OemkeyRevoke
and to get key status. This is port from TGLH platform
implemetation.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
EHL, TGL supports multiple OEM keys and their revocation
by CSE. This patch supports,
- CMDI interface to perform key revocation using
OEMKEYREVOCATION string in cmd file.
- EHL HECI APIs for OemkeyRevoke and to get key status
- FW componets are sorted as per required order.
CSME and BIOS should be signed with new keys and
both components would go together with capsule update.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch fixed a failure in firmware update that
occur during SBL version check. Current code assume
that the SBL layout does not change between the existing
firmware and the capsule, when the layout change, stage1A
address change and this is causing error while obtaining
the firmware version.
Code is modified to use the last 4 bytes of the SBL region
which contain Stage1A FV address and this is used to obtain
the version information.
Signed-off-by: Raghava <raghava.gudla@intel.com>
This adds a common IgdOpRegion library for the same APIs on TGL
and EHL platforms. Plan to include older platforms support in the v2
patch.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
This patch fixed a failure occured during CSME firmware
update. CSME firmware update library expects PCI read buffer
with a specific format, there is mismatch with input and output
parameter with the current code. Added a wrapper function
with the expected format to fix the failure.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
CFL, CML, EHL, TGL platforms are using PSD version 0.3.
as per PSD Spec v0.3 secureboot status indication as ber below,
000 – Secure boot is Disabled
001 – UEFI Secure boot is enabled
010 – Boot Guard is Enabled
100 – Bootloader Verified boot is Enabled
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
During firmware update svn check for SBL region, Current code
assumes that Stage1A base does not change, because of this when
Stage1A base changed in capsule image, getting svn version from
the capsule fails and firmware update is failing.
This patch addressed above issue by reading stage1A base from
capsule image, this way even if stage1A base changes, code will
be able to read it and get svn version from capsule.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
skasim