This commit adds support for PCIe resizable BARsupport.
The feature can be enabled by setting PcdResizableBarSupport
for the board build script and its disabled by default.
Signed-off-by: pastorcx <mariano-paulx.pastorcici@intel.com>
Removed the source code related to TCC tools
including DSO switch, SWSRAM switch, TCC subregions
TCC Error Log switch, RTCM, RTCT
The code change applies on TGL/EHL/ADL/RPL/MTL
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
DebugAgentLib was using its own IDT Entry structure definition that
didn't adjust for x64. Removed this definition and switched to built
in definition from ProcessorBind.h which does adjust for architecture
correctly.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [ADLN] Prevent to enumerate RP25 and above
PCIe RP25 and above are supported only when PCH seriese is PCH S.
Prevent to enumerate RP25 and above to address resource conflict with eMMC.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
* fix: [ADLN] Update eMMC driver strength
Update eMMC driver strength 40Ohm for CRB.
Improve performance benchmark result.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
---------
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
The debug fsp report:
SDI#0: No matching HD-Audio codec verb table found for codec (0x10EC0897).
fix and can see
SDI#0: Detected HD-Audio Codec 0x10EC0897 rev 0x04
Found Verb Table for VendorID 0x10EC, DeviceId 0x0897, RevisionID 0xFF (SDI:FF, size: 4 dwords)
Verified on MCL
Signed-off-by: Randy <randy.lin@intel.com>
Update the option for RVP & LP5 while stitching, add "-o rvp" or "-o lp5" at the end of command
Signed-off-by: Syahirah Sabryna <nur.syahirah.sabryna.mohmad@intel.com>
The "Allow this device to wake the computer" option
(Device Manager => Network adaptors => Properties of PCH GbE
=> Power Management) is grayed out in Windows.
Added the "_PRW" ACPI method to enable the feature.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
The PLATFORM_{NAME} macro is dynamically defined by BuildUtility.py, which
is based on the board file name. Since ASL has been merged into ADL-N, the
PLATFORM_ASL macro has become obsolete and is no longer valid. This commit
removes all instances of the deprecated PLATFORM_ASL.
Additionally, this commit addresses an issue where PLATFORM_ADLN was not
defined in Stage1ABoardInitLib.c during the build process for ADL-N. The cause
was that ConfigDataStruct.h was not included.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
error log:
MdePkg\Library\BaseFdtLib\libfdt\libfdt\fdt_rw.c(194) : error C2220: the following warning is treated as an error
MdePkg\Library\BaseFdtLib\libfdt\libfdt\fdt_rw.c(111) : warning C4706: assignment within conditional expression
MdePkg\Library\BaseFdtLib\libfdt\libfdt\fdt_rw.c(194) : warning C4706: assignment within conditional expression
MdePkg\Library\BaseFdtLib\libfdt\libfdt\fdt_rw.c(89) : error C2220: the following warning is treated as an error
ref: https://learn.microsoft.com/en-us/cpp/error-messages/compiler-warnings/compiler-warning-level-4-c4706?view=msvc-170
Signed-off-by: Randy <randy.lin@intel.com>
BIOS version is NEX ADL-S IPU 2024.4 (5045_03) FSP
FSP version is 0C00D550
platform version is 1.7
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_80_906a3_00000434.pdb', 'm_11_b06e0_00000017.pdb']
Signed-off-by: samihahkasim <samihah.kasim@intel.com>
This patch adjusted MTRR settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used or Fast Boot is enabled.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Check EC device existence before sending command.
The patch prevents waiting for timeout when reading BoardId.
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
The FSP UPD code region should try to cover SBL Stage1A and Stage1B
with a minimum region size. It would impact MTRR settings before memory
init and the MTRR settings would be updated after FspTempRamExit().
Reduce the code region size could improve boot performance for some
SKUs.
Signed-off-by: Guo Dong <guo.dong@intel.com>
When no auth parameter is specified on the command line, gen_layout
chooses auth type based on provided key, but this does not get correctly
applied to the monolithic signing component because of an order of
operations issue.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
When multiple versions of Visual Studio (VS) were installed, the BaseTools
would be built with the latest version, regardless of user preference
(i.e., specified by the "-t" option). This behavior was incorrect for users
needing to build with a specific VS. This commit addresses the issue by aligning
the BaseTools to build with the user-specified version of VS.
Test steps:
0. Two versions of VS are installed: VS2017 and VS2022
1. Default build: python BuildLoader.py build tgl
2. Build with specific version: python BuildLoader.py build tgl -t vs2022
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
BiosRedAssistance setting is added to stitch config.
By default it is disabled. Enable for FW resiliancy.
Signed-off-by: Antara Borwankar <antara.borwankar@intel.com>
Accidental removal of EFIAPI from CalculateRelativePower function in
Stage2BoardInitLib.c caused GCC to issue incompatible-pointer-types error.
This patch addresses the build issue.
Signed-off-by: Ong Ee Lim <ee.lim.ong@intel.com>
Issue: fsp debug log goes to EC port on RVP.
This fix also require FSP update to BIOS version 4053_51 or newer.
Signed-off-by: Randy <randy.lin@intel.com>
FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
- Update Common MeChipsetLib to account for ARLS Me Bus.
Now,the bus number comes from Platform code:
if ARLS bus = 0x80, else bus = 0x0
- Update Heci Pci read calls in HeciMeExtLib to account for
both ARLS and ARL U/H BDF differences.
- Delete ARL specific MeChipset header files as it now uses
common header files from Common Package.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
S0ix failed when NVME attached due to incorrect PCI device configuration
Ported RootPortDownStreamPmConfiguration and related Libraries
To fix incorrect PCIE ASPM and L1 Configuration
Implementation is silicon-dependent due to registers definition
This implementation is using the following ADL PCIE PM PATCH as reference
3bbfe44bec
Signed-off-by: kokweich <kok.wei.chan@intel.com>
Cause by cefbf78dae.
The default build will include the DACM region and the replace file should be present during stitch step.
Add fusa stitch option for users who want to replace that component in the BIOS.
Signed-off-by: Randy <randy.lin@intel.com>
- FSP version is NEX RPL-P MR2 (0C.01.DE.40)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.2
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- Use MeChipsetLib from the Common Soc package and remove
Silicon specific as its redundant
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Pastorcici, Mariano-paulX