TLFS spec defines different hypercall ABIs for X86 and x64. Currently
x64 hypercall interface is not supported well.
Setup the hypercall interface page according to the vcpu mode.
Tracked-On: #5956
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
These two MACROs shall be wrapped as a single
value respectively, hence brackets should be used.
Tracked-On: #5951
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Update missing captions on figures to remove remaining broken references
during latexpdf building. Also, require doing a "make html" before
doing a "make latexpdf" to build all the artifacts needed for running
the latexpdf build. (We might change that later if needed.)
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
In order to support platform (such as Ander Lake) which physical address width
bits is 46, the current code need to reserve 2^16 PD page ((2^46) / (2^30)).
This is a complete waste of memory.
This patch would reserve PD page by three parts:
1. DRAM - may take PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE) PD pages at most;
2. low MMIO - may take PD_PAGE_NUM(MEM_1G << 2U) PD pages at most;
3. high MMIO - may takes (CONFIG_MAX_PCI_DEV_NUM * 6U) PD pages (may plus
PDPT entries if its size is larger than 1GB ) at most for:
(a) MMIO BAR size must be a power of 2 from 16 bytes;
(b) MMIO BAR base address must be power of two in size and are aligned with
its size.
Tracked-On: #5929
Signed-off-by: Li Fei1 <fei1.li@intel.com>
The platform which physical-address width over 39 bits must support
1GB large page (Both MMU and VMX sides ). This could save lots of
page table pages for EPT MMIO mapping.
Tracked-On: #5929
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This patch tweaks the settings in doc/conf.py to allow formatting the
documentation to a PDF file by Sphinx. The changes include:
- Use `xelatex` rather than the default `pdflatex` as the LaTeX engine, as
`pdflatex` is not that good at formatting non-ascii characters out of
the box.
- Use DejaVu fonts (which are available in common Linux distributions) in
the generated PDF.
- Restrict the depths of the table of contents to 3.
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
No one uses get_mem_range_info to get the top/bottom/size of the physical memory.
We could get these informations by e820 table easily.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: eddie Dong <eddie.dong@intel.com>
We used get_mem_range_info to get the top memory address and then use this address
as the high 64 bits max memory address of SOS. This assumes the platform must have
high memory space.
This patch removes the assumption. It will set high 64 bits max memory address of
SOS to 4G by default (Which means there's no 64 bits high memory), then update
the high 64 bits max memory address if the SOS really has high memory space.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: eddie Dong <eddie.dong@intel.com>
SOS's memory size could be calculated by its vE820 Tables easily.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: eddie Dong <eddie.dong@intel.com>
We used get_mem_range_info to get the top memory address and then use this address
as the high 64 bits max memory address. This assumes the platform must have high
memory space.
This patch calculates the high 64 bits max memory address according the e820 tables
and removes the assumption "The platform must have high memory space" by map the
low RAM region and high RAM region separately.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: eddie Dong <eddie.dong@intel.com>
Now BSP may launch VMs before APs have not done its initilization,
for example, sched_control for per-cpu. However, when we initilize
the vcpu thread data, it will access the object (scheduler) of the
sched_control of APs. As a result, it will trigger the PF.
This patch would waits each physical has done its initilization before
to continue to execute.
Tracked-On: #5929
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Using the MFENCE to make sure trampoline code
has been updated (clflush) into memory beforing start APs.
Tracked-On: #5929
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Make the description of the "Logial Partitioning" scenario more
generic than what is shown on the figure. This also helps as the
current examples of that scenario in the code base do not use
Safety or RTVM at the moment (as shown on the picture).
Tracked-On: #5903
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Use MFENCE to strengthen the fast string operations execute order to ensure
all trampoline code was updated before flush it into the memory.
Tracked-On: #5929
Signed-off-by: Li Fei1 <fei1.li@intel.com>
fail to create kata vm type in industry scenario due to
the default vm id value is 1. Meanwhile set the max user
vm to 7 in tgl-rvp industry xml.
Tracked-On: #5932
Signed-off-by: lirui34 <ruix.li@intel.com>
There is no audio device in the default ehl-crb-b.xml, so remove
passthru audio devices from launch xmls on ehl-crb-b.
Tracked-On: #5925
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
remove UOS_RAM_SIZE and SOS_RAM_SIZE in scenario config since these
two config elements are useless.
Tracked-On: #5927
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
update HV_RAM_SIZE calculation algorithm to 20MB + VM number*
16MB, which consists of text segment rodata(2MB), bss data(about
1MB), bss.ppt_pages(2.4MB), bss.ctx_tables(6MB), bss.vm_array(
3.2MB), bss.ivshmem_base(2MB+1.8MB for alignment) and
bss.post_uos_sworld_memory(16MB*post-launched VM number).
Tracked-On: #5927
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
We've validated doc build tool versions, so let's make sure those are
the versions the instructions say to install. The version of doxygen
you get when you use ``sudo apt install doxygen`` may get a newer
version that may still work so let's tell them that.
Also, we no longer use kconfig files in the document build process, so
remove mentioning that in the build documentation.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Refine the logic of finding unused bdf for SOS ivshmem devices. First,
find the unused bdf based on if the "dev" is unused. Increase the "func"
for the next same type of emulated devices if the last assigned bdf
exists. Otherwise, start over looking for unused bdf based on "dev"
repeatedly.
Tracked-On: #5869
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
The ACRN configuration option details are no longer maintained in a
checked-in document. Instead they are generated during the
``make html`` from information in the schema .xsd files.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Windows graphic driver obtains DSM address from in-BAR mmio register
which has passthroughed. Not like the other platforms obtained from
pci configure space register which has virtualized. GPU GuC must use
WOPCM in DSM, besides, Windows OS wants to manage DSM also. These two
reason force acrn has to keep identical mapping to avoid trap mmio
BAR to do the emulation.
Tracked-On: #5880
Signed-off-by: Peng Sun <peng.p.sun@intel.com>
For platform with HLAT (Hypervisor-managed Linear Address Translation)
capability, the hypervisor shall hide this feature to its guest.
This patch adds MSR_IA32_VMX_PROCBASED_CTLS3 MSR to unsupported MSR
list.
The presence of this MSR is determined by 1-setting of bit 49 of MSR
MSR_IA32_VMX_PROCBASED_CTLS. which is already in unsupported MSR list. [2]
Related documentations:
[1] Intel Architecture Instruction Set Extensions, version Feb 16, 2021,
Ch 6.12
[2] Intel KeyLocker Specification, Sept 2020, Ch 7.2
Tracked-On: #5895
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
- use one command to generate x509 cert file,
remove the intermediate file.
- remove the "Keycontainer" field in INF file,
which is not mandatory.
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Remove the Power Management ('pm') parameters from the sample launch scripts,
and update the comments, At most one VM is allowed to use "--pm_notify_channel uart"
at a time, since only one socket connection to SOS life_mngr is allowed.
Remove it by default and allow user to add on demand
rt_industry_ubuntu.rst
enable_s5.rst
Signed-off-by: li shuang <shuangx.li@intel.com>
Update draft release notes with more information about documentation.
Remove code-block extra indenting.
Add label to roscube gsg so we can link to it (in the releaes notes).
Fix style for :option: references to make them look more links links.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Instruct the user to create a copy of the scenario XML file if modifications
are needed. That modified copy should subsequently be used for building ACRN.
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Update the ACPI Component Architecture package (acpica-unix) to
the latest version available as of today: 20210105
Tracked-On: #5553
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
v2:
* Add the complete instructions to upgrade Python
* Add libxml2-utils as another additional tool required for building v2.4
* Random typo fixes
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Signed-off-by: Benjamin Fitch <benjamin.fitch@intel.com>
This patch adds the following dependencies among recipes:
- Building of any C file depends on $(HV_CONFIG_TIMESTAMP) which indicates
the presence of generated configuration files.
- Source files listed in $(VM_CFG_C_SRCS), which are the generated
configuration files, depends on $(HV_CONFIG_TIMESTAMP)
With the dependencies above, the build system can now safely be executed in
parallel, e.g. `make -j4`.
Tracked-On: #5874
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The ACRN life_mngr is not built by default as it is a component
that will run in the User VM. Instead we create a 'life_mngr'
(and 'life_mngr-install') targets to build it individually from
the top-level folder.
Tracked-On: #5660
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Do not build (or install) the ACRN life_mngr by default as this is
a User VM tool, not one to be used and run in the Service VM.
The component can still be built independantly by invoking
'make -C misc life_mngr' (components will be built and placed in
'misc/build/services/' by default).
Tracked-On: #5660
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
sanitize_pte is used to set page table entry to map to an sanitized page to
mitigate l1tf. It should belongs to pgtable module. So move it to pagetable.c
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
lookup_address is used to lookup a pagetable entry by an address. So rename it
to pgtable_lookup_entry to indicate this clearly.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
alloc_page/free_page should been called in pagetable module. In order to do this,
we add pgtable_create_root and pgtable_create_trusty_root to create PML4 page table
page for normal world and secure world.
After this done, no one uses alloc_ept_page. So remove it.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Add pgtable_create_trusty_root to allocate a page for trusty PML4 page table page.
This function also copy PDPT entries from Normal world to Secure world.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Add pgtable_create_root to allocate a page for PMl4 page table page.
Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Jian Jun Chen