864 lines
18 KiB
C
864 lines
18 KiB
C
/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef INTEL_COMM_WIDGET_H
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#define INTEL_COMM_WIDGET_H
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#include <zephyr/cache.h>
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#include <zephyr/kernel.h>
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#define CW_DT_NODE DT_NODELABEL(ace_comm_widget)
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#define CW_BASE DT_REG_ADDR(CW_DT_NODE)
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/*
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* @brief DSP Communication Widget for Intel ADSP
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*
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* These registers control the DSP Communication Widget for generic sideband message transmit /
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* receive.
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*/
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/*
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* Downstream Attributes
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* Attribute register for downstream message.
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*/
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#define DSATTR 0x00
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/*
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* Destination Port ID
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* type: RO/V, rst: 00h
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*
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* Destination Port ID received in message.
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*/
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#define DSATTR_DSTPID GENMASK(7, 0)
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/*
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* Source Port ID
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* type: RO/V, rst: 00h
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*
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* Source Port ID received in message.
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*/
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#define DSATTR_SRCPID GENMASK(15, 8)
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/*
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* Opcode
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* type: RO/V, rst: 00h
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*
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* Opcode received in message.
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*/
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#define DSATTR_OPC GENMASK(23, 16)
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/*
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* Byte Enable
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* type: RO/V, rst: 0h
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*
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* Byte enables received in message.
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*/
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#define DSATTR_BE GENMASK(27, 24)
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/*
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* Reserved
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* type: RO, rst: 0h
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*/
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#define DSATTR_RSVD31 GENMASK(31, 28)
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/*
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* Downstream Lower Address
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* Address register (lower 32 bits) for downstream message.
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*
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* type: RO/V, rst: 0000 0000h
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*
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* LSB 32 address bits received in message. Bits 32:16 of the LSB address only
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* valid when DSUADDR.ADDRLEN bit is set to 1.
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*/
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#define DSLADDR 0x04
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/*
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* Downstream Upper Address
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* Address register (upper 32 bits) for downstream message.
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*/
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#define DSUADDR 0x08
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/*
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* Upper Address
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* type: RO/V, rst: 0000h
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*
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* MSB 16 address bits received in message. Valid only when ADDRLEN bit is set to 1.
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*/
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#define DSUADDR_UADDR GENMASK(15, 0)
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/*
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* Reserved
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* type: RO, rst: 0000h
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*/
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#define DSUADDR_RSVD30 GENMASK(30, 16)
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/*
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* Address Length
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* type: RO/V, rst: 0b
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*
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* Address length indication received in message.
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* 0: 16-bit address
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* 1: 48-bit address
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*/
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#define DSUADDR_ADDRLEN BIT(31)
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/*
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* Downstream SAI
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* Extended header (SAI / RS) register for downstream message.
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*/
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#define DSSAI 0x0C
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/*
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* SAI
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* type: RO/V, rst: 0000h
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*
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* SAI received in message. Valid if EHP bit set to 1.
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*/
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#define DSSAI_SAI GENMASK(15, 0)
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/*
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* Root Space
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* type: RO/V, rst: 0h
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*
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* Root space received in message. Valid if EHP bit set to 1.
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*/
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#define DSSAI_RS GENMASK(19, 16)
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/*
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* Reserved
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* type: RO, rst: 000h
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*/
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#define DSSAI_RSVD30 GENMASK(30, 20)
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/*
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* Extended Header Present
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* type: RO/V, rst: 0b
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*
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* Extended header present indication received in message. When set to 1 indicates
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* extended header is present, and RS / SAI fields are valid.
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*/
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#define DSSAI_EHP BIT(31)
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/*
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* Downstream Data
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* Receive data register for downstream message.
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*
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* type: RO/V, rst: 0000 0000h
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*
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* Data received in message.
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*/
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#define DSDATA 0x10
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/*
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* Downstream Control & Status
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* Control & status register for downstream message.
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*/
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#define DSCTLSTS 0x14
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/*
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* Transaction Type
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* type: RO/V, rst: 00b
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*
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* Indicates type of transaction received as follows:
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* 01: Posted message
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* 10: Non-posted message
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* 11: Completion message.
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*/
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#define DSCTLSTS_TRANTYP GENMASK(1, 0)
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/*
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* Reserved
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* type: RO, rst: 000 0000h
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*/
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#define DSCTLSTS_RSVD29 GENMASK(29, 2)
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/*
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* Interrupt GENMASK
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* Interrupt GENMASK register for message received interrupt. When set to 1 interrupt
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* is not generated to DSP Core. GENMASK does not affect interrupt status bit.
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*/
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#define DSCTLSTS_IM BIT(30)
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/*
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* Message Received
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* type: RO/V, rst: 0b
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*
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* Message received interrupt status register. Set by HW when message is received,
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* and cleared by HW when FW writes to upstream completion control register
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* indicating completion is available.
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*/
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#define DSCTLSTS_MSGRCV BIT(31)
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/*
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* Downstream Source Port ID
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* Source port ID register for ACE IP.
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*/
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#define ACESRCPID 0x18
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/*
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* Source Port ID
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* type: RO/V, rst: ACE_SRCID
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*
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* Source Port ID of ACE IP. Default value is hardcoded to parameter ACE_SRCID.
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*/
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#define ACESRCPID_SRCPID GENMASK(7, 0)
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/*
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* Reserved
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* type: RO, rst: 00 0000h
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*/
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#define ACESRCPID_RSVD31 GENMASK(31, 8)
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/*
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* Downstream Completion Data
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*
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* type: RO/V, rst: 0000 0000h
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*
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* Completion data received for upstream non-posted read.
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*/
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#define DSCPDATA 0x20
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/*
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* Downstream Completion SAI
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*
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* type: RO/V, rst: 0000 0000h
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*
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* Completion SAI received for upstream non-posted message.
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*/
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#define DSCPSAI 0x24
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/*
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* Downstream Completion Control & Status
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*/
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#define DSCPCTLSTS 0x28
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/*
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* Completion Status
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* type: RO/V, rst: 0b
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*
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* Completion status received for upstream non-posted message
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* 000: Successful Completion (SC)
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* 001: Unsupported Request (UR).
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*/
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#define DSCPCTLSTS_CPSTS GENMASK(2, 0)
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/*
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* Reserved
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* type: RO, rst: 0b
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*/
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#define DSCPCTLSTS_RSVD7 GENMASK(7, 3)
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/*
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* Completion Extended Header Present
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* type: RO/V, rst: 0b
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*
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* Completion EH present indication received for upstream non-posted message.
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*/
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#define DSCPCTLSTS_CPEHP BIT(8)
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/*
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* Reserved
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* type: RO, rst: 00 0000h
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*/
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#define DSCPCTLSTS_RSVD29 GENMASK(29, 9)
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/*
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* Interrupt GENMASK
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* Interrupt GENMASK register for completion received interrupt. When set to 1
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* interrupt is not generated to DSP Core. GENMASK does not affect interrupt status
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* bit.
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*/
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#define DSCPCTLSTS_IM BIT(30)
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/*
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* Completion Received
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* type: RW/1C, rst: 0b, rst domain: gHSTRST
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*
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* Completion received status register. Set by HW when completion is received, and
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* cleared by FW when writing 1 to it.
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*/
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#define DSCPCTLSTS_CPRCV BIT(31)
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/*
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* Upstream Status
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* Status register for upstream message.
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*/
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#define USSTS 0x40
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/*
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* State Machine Status
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* type: RO/V, rst: 0b
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*
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* 0: The Endpoint Status Machine is idle
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* 1: The Endpoint State Machine is busy
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* This is OR of posted SM and non-posted SM busy signals.
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*/
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#define USSTS_SMSTS BIT(0)
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/*
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* Message Sent
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* type: RW/1C, rst: 0b, rst domain: gHSTRST
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*
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* Upstream message sent interrupt status. Set by HW when upstream message has been
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* sent out, and cleared by FW when writing 1 to it.
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*/
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#define USSTS_MSGSENT BIT(1)
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/*
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* Reserved
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* type: RO, rst: 0000 0000h
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*/
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#define USSTS_RSVD31 GENMASK(31, 2)
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/*
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* Upstream Command
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* Command register for upstream message.
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*/
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#define USCMD 0x44
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/*
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* Send Sideband Transaction
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* type: WO, rst: 0b
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*
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* DSP FW writes a 1 to this bit to cause an IOSF SB Transaction. The type of
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* transaction is determined by Bit 1 in this register. This bit will always be
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* read as 0 but FW can write it to 1 to start the upstream transaction. In that way
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* it won't be readable as 1 after writing to. The write to this bit is ignored by
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* hardware if opcode is 0x20 - 0x2F.
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*/
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#define USCMD_SSBTRAN BIT(0)
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/*
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* Transaction Type
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* 0: Transaction will be a Write
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* 1: Transaction will be a Read
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* For posted message this register bit value will be ignored and hardcoded to 0 in
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* the actual message as reads cannot be posted.
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*/
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#define USCMD_TRANTYP BIT(1)
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/*
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* Message Type
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* 0: Transaction will be non-posted
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* 1: Transaction will be posted
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*/
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#define USCMD_MSGTYP BIT(2)
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/*
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* Interrupt Enable
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* Interrupt enable register for message sent interrupt. When cleared to 0 interrupt
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* is not generated to DSP Core. Enable does not affect interrupt status bit.
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*/
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#define USCMD_IE BIT(3)
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/*
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* Reserved
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* type: RO, rst: 000 0000h
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*/
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#define USCMD_RSVD31 GENMASK(31, 4)
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/*
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* Upstream Lower Address
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* Address register (lower 32 bits) for upstream message.
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*
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* type: RW, rst: 0000 0000h, rst domain: gHSTRST
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*
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* LSB 32 address bits for message to be sent. Bits 32:16 of the LSB address only
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* valid when USUADDR.ADDRLEN bit is set to 1.
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*/
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#define USLADDR 0x48
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/*
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* Upstream Upper Address
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* Address register (upper 32 bits) for upstream message.
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*/
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#define USUADDR 0x4C
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/*
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* Upper Address
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* type: RW, rst: 0000h, rst domain: gHSTRST
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*
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* MSB 16 address bits for message to be sent. Valid only when ADDRLEN bit is set
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* to 1.
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*/
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#define USUADDR_UADDR GENMASK(15, 0)
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/*
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* Reserved
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* type: RO, rst: 0000h
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*/
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#define USUADDR_RSVD30 GENMASK(30, 16)
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/*
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* Address Length
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* Address length indication for message to be sent.
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* 0: 16-bit address
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* 1: 48-bit address
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* For simple message / message with data, this field will carry the MISC[3] of the
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* IOSF 1.2 message format.
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*/
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#define USUADDR_ADDRLEN BIT(31)
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/*
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* Upstream Data
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* Transmit data register for upstream message.
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*
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* type: RW, rst: 0000 0000h, rst domain: gHSTRST
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*
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* Data for message to be sent.
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*/
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#define USDATA 0x50
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/*
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* Upstream Attributes
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* Attribute register for upstream message.
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*/
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#define USATTR 0x54
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/*
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* Destination Port ID
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* type: RW, rst: 00h, rst domain: gHSTRST
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*
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* Destination ID for message to be sent.
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*/
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#define USATTR_DSTPID GENMASK(7, 0)
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/*
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* Opcode
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* type: RW, rst: 00h, rst domain: gHSTRST
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*
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* Opcode for message to be sent.
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*/
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#define USATTR_OPC GENMASK(15, 8)
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/*
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* Byte Enable
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* type: RW, rst: 0h, rst domain: gHSTRST
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*
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* Byte enables for message to be sent.
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*/
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#define USATTR_BE GENMASK(19, 16)
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/*
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* Base Address Register
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* type: RW, rst: 0h, rst domain: gHSTRST
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*
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* BAR for register access to be sent. For simple message / message with data, this
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* field will carry the MISC[2:0] of the IOSF 1.2 message format. Note: MSB of this
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* register field is not used given the IOSF Sideband message BAR field is ONLY 3
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* bits wide; and MISC[3] of the IOSF 1.2 message format is supplied by
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* USUADDR.ADDRLEN.
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*/
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#define USATTR_BAR GENMASK(23, 20)
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/*
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* Function ID
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* type: RW, rst: 00h, rst domain: gHSTRST
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*
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* Function ID for register access to be sent.
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*/
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#define USATTR_FID GENMASK(31, 24)
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/*
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* Upstream SAI
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* Extended header (SAI / RS) register for upstream message.
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*/
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#define USSAI 0x58
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/*
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* SAI
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* type: RO, rst: DSPISAI_2SB
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*
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* SAI for message to be sent, if EHP bit set to 1. Reset value is hardcoded to
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* parameter DSPISAI_2SB.
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*/
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#define USSAI_SAI GENMASK(7, 0)
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/*
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* Reserved
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* type: RO, rst: 00h
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*/
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#define USSAI_RSVD15 GENMASK(15, 8)
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/*
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* Root Space
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* type: RW, rst: 0h, rst domain: gHSTRST
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*
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* Root space for message to be sent, if EHP bit set to 1.
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*/
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#define USSAI_RS GENMASK(19, 16)
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/*
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* Reserved
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* type: RO, rst: 000h
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*/
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#define USSAI_RSVD30 GENMASK(30, 20)
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/*
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* Extended Header Present
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* type: RO, rst: 1b
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*
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* Extended header present indication for message to be sent. When set to 1
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* indicates extended header is present. Currently tied to 1 in RTL as ACE IP
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* supports only EH=1 transactions.
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*/
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#define USSAI_EHP BIT(31)
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/*
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* Upstream Completion Data
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*
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* type: RW, rst: 0000 0000h, rst domain: gHSTRST
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*
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* Completion data to be sent for downstream non-posted read.
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*/
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#define USCPDATA 0x5C
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/*
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* Upstream Completion Control & Status
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*/
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#define USCPCTLSTS 0x60
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/*
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* Completion Status
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* type: RW, rst: 0h, rst domain: gHSTRST
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*
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* Completion status to be sent for downstream non-posted message.
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* 000: Successful Completion (SC)
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* 001: Unsupported Request (UR).
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*/
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#define USCPCTLSTS_CPSTS GENMASK(2, 0)
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/*
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* Reserved
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* type: RO, rst: 000 0000h
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*/
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#define USCPCTLSTS_RSVD30 GENMASK(30, 3)
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/*
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* Sideband Completion
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* type: RW/1S, rst: 0h, rst domain: gHSTRST
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*
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* Completion for downstream request handling. DSP FW writes a 1 to this bit to
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* indicate downstream message received is consumed. This internally causes an IOSF
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* SB completion transaction if original downstream request is non-posted. If
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* original message is posted then upstream completion is not generated by HW. This
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* bit is cleared by HW.
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*/
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#define USCPCTLSTS_SBCP BIT(31)
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/*
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* Upstream completion SAI
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*/
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#define USCPSAI 0x64
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/*
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* SAI
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* type: RO, rst: DSPISAI_2SB
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*
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* Completion SAI to be sent for downstream non-posted message. Reset value is
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* hardcoded to parameter DSPISAI_2SB.
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*/
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#define USCPSAI_CPSAI GENMASK(7, 0)
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/*
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* Reserved
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* type: RO, rst: 00h
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*/
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#define USCPSAI_RSVD15 GENMASK(15, 8)
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/*
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* Spare 1
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* type: RW, rst: 0h, rst domain: gHSTRST
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*
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* 4 Spare bits.
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*/
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#define USCPSAI_SPARE1 GENMASK(19, 16)
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/*
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* Reserved
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* type: RO, rst: 000h
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*/
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#define USCPSAI_RSVD30 GENMASK(30, 20)
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/*
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* Spare 0
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* type: RW, rst: 0b, rst domain: gHSTRST
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*
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* 1 Spare bit.
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*/
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#define USCPSAI_SPARE0 BIT(31)
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/*
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* SAI Width
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*/
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#define SAIWDTH 0x68
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/*
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* SAI Width
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* type: RO, rst: SAI_WIDTH
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*
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* Specifies the SAI width value.
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* 0-based value.
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*/
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#define SAIWDTH_SAIWDTH GENMASK(3, 0)
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/*
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* Reserved
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* type: RO, rst: 000 0000h
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*/
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#define SAIWDTH_RSVD31 GENMASK(31, 4)
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|
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/*
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* Side Clock Gate
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* Sideband clock gating enable register.
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*/
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#define SCLKG 0x6C
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/*
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* Local Clock Gate
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* type: RW, rst: 0b, rst domain: gHSTRST
|
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*
|
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* 0: Clk is un-gated
|
|
* 1: Clk is gated
|
|
* Implementation Note: Local clock gating is not implemented as there are only ~10
|
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* flops in the design.
|
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*/
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#define SCLKG_LCG BIT(0)
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|
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/*
|
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* Trunk Clock Gate
|
|
* type: RW, rst: 0b, rst domain: gHSTRST
|
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*
|
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* 0: Clk request enabled
|
|
* 1: Clk is gated
|
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* Implementation Note: This FW managed TCG bit is not used as HW has been improved
|
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* to support trunk clock gating based on FSM operation.
|
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*/
|
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#define SCLKG_TCG BIT(1)
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|
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/*
|
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* Reserved
|
|
* type: RO, rst: 0000 0000h
|
|
*/
|
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#define SCLKG_RSVD31 GENMASK(31, 2)
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|
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|
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/*
|
|
* Downstream Data 2
|
|
* Receive data (second DW) register for downstream message.
|
|
*
|
|
* type: RW, rst: 0000 0000h, rst domain: gHSTRST
|
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*
|
|
* Data received in message. Second DW, if valid.
|
|
*/
|
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#define DSDATA2 0x74
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|
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|
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/*
|
|
* Downstream Access Enable
|
|
*
|
|
* Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
|
|
* model in ACE IP to support any boot prep message handling by FW.
|
|
*/
|
|
#define DSACCEN 0x80
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|
|
|
/*
|
|
* Access Enable
|
|
* type: RW, rst: 0b, rst domain: gHSTRST
|
|
*
|
|
* This bit is set by DSP FW to enable SBEP HW to accept downstream cycles from
|
|
* Sideband peer agents (as well as access control policy owner for survivability).
|
|
* NOTE: If a BOOTPREP message is received, DSP FW is interrupted unconditionally,
|
|
* i.e. irrespective of this bit being 1 or 0.
|
|
*/
|
|
#define DSACCEN_ACCEN BIT(0)
|
|
|
|
/*
|
|
* Reserved
|
|
* type: RO, rst: 0000 0000h
|
|
*/
|
|
#define DSACCEN_RSVD31 GENMASK(31, 1)
|
|
|
|
|
|
/*
|
|
* Boot Prep Control
|
|
* Boot prep message control register.
|
|
* Note: boot prep handling is an artifact of re-using the component from ISH. There is no usage
|
|
* model in ACE IP to support any boot prep message handling by FW.
|
|
*/
|
|
#define BPCTL 0x84
|
|
|
|
/*
|
|
* type: RW/1C, rst: 0b, rst domain: gHSTRST
|
|
* Boot Prep Received Status
|
|
*
|
|
* This bit is set by SBEP HW upon the reception of BOOTPREP message. DSP FW is
|
|
* required to clear this status bit by writing a 0 to the bit, upon issuing
|
|
* BOOTPREPACK message on the upstream path of SBEP HW. SBEP HW will clear this bit,
|
|
* upon auto ack'ing of BOOTPREP due to timeout condition.
|
|
*/
|
|
#define BPCTL_BPRCVSTS BIT(0)
|
|
|
|
/*
|
|
* Reserved
|
|
* type: RO, rst: 0000 0000h
|
|
*/
|
|
#define BPCTL_RSVD31 GENMASK(31, 1)
|
|
|
|
|
|
#define CW_TRANSACTION_NONPOSTED 0
|
|
#define CW_TRANSACTION_POSTED 1
|
|
|
|
#define CW_TRANSACTION_WRITE 0
|
|
#define CW_TRANSACTION_READ 1
|
|
|
|
/*
|
|
* @brief Check the endpoint state machine is idle
|
|
*
|
|
* @retval false The Endpoint State Machine is busy
|
|
* @retval true The Endpoint State Machine is idle
|
|
*/
|
|
static inline bool cw_upstream_ready(void)
|
|
{
|
|
uint32_t status = sys_read32(CW_BASE + USSTS);
|
|
|
|
status &= ~USSTS_SMSTS;
|
|
sys_write32(status, CW_BASE + USSTS);
|
|
return !(sys_read32(CW_BASE + USSTS) & USSTS_SMSTS);
|
|
}
|
|
|
|
/*
|
|
* @brief Configure attributes of upstream message
|
|
*
|
|
* @param dest Destination Port ID for message to be sent.
|
|
* @param func Function ID for register access to be sent.
|
|
* @param opcode Opcode for message to be sent.
|
|
* @param be Byte enables for message to be sent.
|
|
* @param bar Base Address Register for register access to be sent.
|
|
*/
|
|
static inline void cw_upstream_set_attr(uint32_t dest, uint32_t func, uint32_t opcode,
|
|
uint32_t be, uint32_t bar)
|
|
{
|
|
uint32_t attr = FIELD_PREP(USATTR_DSTPID, dest) | FIELD_PREP(USATTR_FID, func) |
|
|
FIELD_PREP(USATTR_OPC, opcode) | FIELD_PREP(USATTR_BE, be) |
|
|
FIELD_PREP(USATTR_BAR, bar);
|
|
sys_write32(attr, CW_BASE + USATTR);
|
|
}
|
|
|
|
/*
|
|
* @brief Set 16bit address for upstream message.
|
|
*
|
|
* @param address Address for message to be sent.
|
|
*/
|
|
static inline void cw_upstream_set_address16(uint16_t address)
|
|
{
|
|
sys_write32(address, CW_BASE + USLADDR);
|
|
sys_write32(0, CW_BASE + USUADDR);
|
|
}
|
|
|
|
/*
|
|
* @brief Set transmit data for upstream message.
|
|
*
|
|
* @param data Data for message to be sent.
|
|
*/
|
|
static inline void cw_upstream_set_data(uint32_t data)
|
|
{
|
|
sys_write32(data, CW_BASE + USDATA);
|
|
}
|
|
|
|
/*
|
|
* @brief Interrupt enable / disable for message sent interrupt.
|
|
*
|
|
* @param enable Interrupt state
|
|
*/
|
|
static inline void cw_upstream_enable_sent_intr(bool enable)
|
|
{
|
|
uint32_t cmd = sys_read32(CW_BASE + USCMD);
|
|
|
|
if (enable) {
|
|
cmd |= USCMD_IE;
|
|
} else {
|
|
cmd &= ~USCMD_IE;
|
|
}
|
|
|
|
sys_write32(cmd, CW_BASE + USCMD);
|
|
}
|
|
|
|
/*
|
|
* @brief Write posted message.
|
|
*/
|
|
static inline void cw_upstream_do_pw(void)
|
|
{
|
|
uint32_t cmd = sys_read32(CW_BASE + USCMD);
|
|
|
|
cmd &= ~(USCMD_MSGTYP | USCMD_TRANTYP);
|
|
cmd |= FIELD_PREP(USCMD_MSGTYP, CW_TRANSACTION_POSTED) |
|
|
FIELD_PREP(USCMD_TRANTYP, CW_TRANSACTION_WRITE) |
|
|
USCMD_SSBTRAN;
|
|
|
|
sys_write32(cmd, CW_BASE + USCMD);
|
|
}
|
|
|
|
/*
|
|
* @brief Clear message send interrupt status
|
|
*/
|
|
static inline void cw_upstream_clear_msgsent(void)
|
|
{
|
|
uint32_t sts = sys_read32(CW_BASE + USSTS);
|
|
|
|
sts |= USSTS_MSGSENT;
|
|
sys_write32(sts, CW_BASE + USSTS);
|
|
}
|
|
|
|
/*
|
|
* @brief Wait for message to be send.
|
|
*/
|
|
static inline void cw_upstream_wait_for_sent(void)
|
|
{
|
|
WAIT_FOR(sys_read32(CW_BASE + USSTS) & USSTS_MSGSENT, 100, k_busy_wait(1));
|
|
|
|
cw_upstream_clear_msgsent();
|
|
}
|
|
|
|
/*
|
|
* @brief Write a sideband message.
|
|
*/
|
|
void cw_sb_write(uint32_t dest, uint32_t func, uint16_t address, uint32_t data);
|
|
|
|
|
|
#endif /* INTEL_COMM_WIDGET_H */
|