65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Macros for power gating memory banks specific for ACE 1.0
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*/
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#ifndef __ZEPHYR_ACE_LIB_ASM_MEMORY_MANAGEMENT_H__
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#define __ZEPHYR_ACE_LIB_ASM_MEMORY_MANAGEMENT_H__
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#include <zephyr/devicetree.h>
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#ifdef _ASMLANGUAGE
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.macro m_ace_lpsram_power_down_entire ax, ay, az, au
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/* Retrieve the LPSRAM bank count from the ACE_L2MCAP register */
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movi \az, DT_REG_ADDR(DT_NODELABEL(hsbcap))
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l32i \az, \az, 0
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/* Extract the 4-bit bank count field starting from bit 8 */
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extui \au, \az, 8, 4
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movi \ay, 1 /* Power down command */
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/* Get the address of the LPSRAM control register from the Devicetree */
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movi \az, DT_REG_ADDR(DT_NODELABEL(lsbpm))
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2 :
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/* Issue the power down command to the current LPSRAM bank */
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s8i \ay, \az, 0
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memw
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1 :
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/* Poll the status register to confirm the power down command has taken effect */
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l8ui \ax, \az, 4
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bne \ax, \ay, 1b
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/* Move to the next LPSRAM bank control register */
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addi \az, \az, DT_REG_SIZE(DT_NODELABEL(lsbpm))
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addi \au, \au, -1 /* Decrement bank count */
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bnez \au, 2b /* If banks are left, continue loop */
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.endm
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.macro m_ace_hpsram_power_down_entire ax, ay, az, au
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/* Read the HPSRAM bank count from ACE_L2MCAP register */
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movi \au, DT_REG_ADDR(DT_NODELABEL(hsbcap))
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l32i \au, \au, 0
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extui \au, \au, 0, 8 /* Bank count is in the lower 8 bits */
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movi \ay, 1 /* Power down command */
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/* Calculate the address of the HSxPGCTL register */
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movi \az, DT_REG_ADDR(DT_NODELABEL(hsbpm))
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2 :
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s8i \ay, \az, 0 /* HSxPGCTL.l2lmpge = 1 (power down) */
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memw
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1 :
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l8ui \ax, \az, 4 /* ax = HSxPGISTS.l2lmpgis */
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bne \ax, \ay, 1b /* wait till status == request */
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addi \az, \az, DT_REG_SIZE(DT_NODELABEL(hsbpm)) /* Move to next bank control register */
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addi \au, \au, -1 /* Decrement bank count */
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bnez \au, 2b /* If banks are left, continue loop */
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.endm
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#endif /* _ASMLANGUAGE */
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#endif /* __Z_ACE_LIB_ASM_MEMORY_MANAGEMENT_H__ */
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