Implements copy functions from/to DMA buffer. They take care
of cache operations and also can perform custom processing
during copy. By default it will be usual buffer copy, but in the future
it can be replaced with pcm conversions, so we don't need volume
into the pipelines just for that operation.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds new DMA attribute DMA_ATTR_BUFFER_PERIOD_COUNT and implements
it for every DMA. This attribute says how many periods should DMA
buffer consist of.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Adds and initializes id, pipeline_id and caps fields in buffer struct.
This is the only data needed after buffer creation. It allows us to
remove the whole sof_ipc_buffer struct from the buffers.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
The ESAI is a hardware DAI on the i.MX platform. This commit brings the
initial support for the ESAI.
For now, the hardware FIFO watermark is hardcoded to 96 which means that
DMA transfers will be initiated when 96 of the 128 FIFO slots are empty.
IRQ handling is disabled (but possibly not needed anyway) and the clock
divider settings are hardcoded and correct for MCLK of 49152000 Hz,
48000 Hz sample rate, 2 channels, 32-bit samples (for the codec).
See https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf, pages
7435-7506 (ESAI).
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Add mute switch with led control to capture playback pipeline's volume
component. This will show in user space alsa controls as 1 element with
2 controls (volume and mute switch). Some user space audio software like
this a lot.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
Add optional mute led token support to mixer control. Optional
parameters at the end of mixer control macro will add mute led tokens
and related parameters to the private data section.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
Add tokens to topology for led use and led direction. Led use is true
for positive integers, false for 0. Led direction 0 corresponds to
playback and positive integers to capture.
Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
This improves the performance quite significantly -- pipeline_copy on
the simple ESAI pipeline (the cs42888 pipeline) took around 781us before
while with caching I got times of 15us at a minimum (a 50-fold
improvement).
Values:
-> 0x40000000-0x5FFFFFFF: 2 (bypass, contains ADMA registers)
-> 0x80000000-0x9FFFFFFF: 1 (write-through, write allocate). This
contains almost all of the code in 0x92400000-0x92BFFFFF and all the
heaps in 0x92C00000-0x933FFFFF.
-> Everything else has cache bypass (Dummy DMA needs to be able to use
host buffers from wherever)
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
The semantics of a DMA driver is to transfer data to/from RAM rather
than to/from the DSP cache. As such I need to flush the cache before
and after the copy (see comments inline).
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Power gating for HPSRAM & LPSRAM on D3 entry enabled for all cAVS
platforms (cAVS 1.5/1.8/2.x) except SueCreek. Implementation shared
between cAVS 1.8/2.0/2.5 is located in cavs lib, cAVS 1.5 specific
implementation remains in ApolloLake platform directory.
Signed-off-by: Lech Betlej <lech.betlej@linux.intel.com>
cAVS power down sequence refactored by moving CannonLake (cAVS 1.8)
implementation to cavs lib as a base for cAVS 1.8/2.0/2.5 common
code. ApolloLake (cAVS 1.5) specific implementation remains as a
platform specific code.
Signed-off-by: Lech Betlej <lech.betlej@linux.intel.com>
The number of bytes copied at each ieration must
match half the total size copied as we have an
interrupt at HALF and MAJOR loop
Signed-off-by: Guido Roncarolo <guido.roncarolo@nxp.com>
Signed-off-by: Jerome Laclavere <jerome.laclavere@nxp.com>
burst_size represents the FIFO width in words, translate it
into bytes to have homogeneous quantities
Signed-off-by: Guido Roncarolo <guido.roncarolo@nxp.com>
This patch slightly modifies draining speed algorithm.
Instead of copying half the buffer each period we
copy two periods. This slightly decreases draining
speed but avoids XRUNs in rare cases.
Signed-off-by: Marcin Rajwa <marcin.rajwa@linux.intel.com>
Fix the copy/paste errors in naming the keyword-detect
pipeline connections for CML and GLK.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Fixes race condition in low latency scheduler when multiple cores
are processing tasks on the same scheduling domain. Task's start
time is updated based on last_tick right after the task is finished.
Last_tick can be updated in the meantime by other core in the situation,
where it starts handling interrupt later, but finishes its tasks
earlier.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Chirp test signals confused the test signal begin marker position
seek and caused false test fails. The test stimulus may produce
stronger cross correlation level than the actual marker. Also
the check omitted that the cross correlation max could be negative
so the test was changed into power domain and use first/last
cross correlation peak above threshold as test begin/end position.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Gain of SRC varies by 1 dB due built-in attenuation in the filter
coefficients. It was added to avoid signal overshoots to distort
with some challenging music content. When a converter consists of
two filters in series the attenuation duplicates. While SRC is
missing the gain compensation the test criteria needs to be relaxed.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
The introduction of the DMA multi channel domain made it so the cascaded
interrupt handling fails to allocate memory from this heap. Increasing
the size of the system runtime heap will allow the registering of
cascaded interrupts (and in particular the EDMA interrupt within the DMA
scheduling domain) to continue.
On this platform we have 8MB of total memory. Allocating 24kB instead of
12kB for the system runtime heap does not cause any noticeable change
besides removing the memory allocation failures.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Merged hp buffer heap with normal buffer heap.
Since current buffer heap was actually using hp memory and it served
no purpose to have two heaps.
Removed extern capabilities and merged other capabiliteis to
buffer heap. Currently none of those buffer heaps supports extern.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This patch adds topology sof-apl-src-dmic.m4 to test capture SRC.
The topology instantiates SRCs for 48 -> 8-48 kHz and 16 -> 8-48 kHz
capture. The volume component in pipeline handles PCM format
conversion from the fixed S32_LE DMIC DAI format. Also the bugs in
the earlier non-used pipeline macro are fixed.
The macro pipe-src-capture.m4 is renamed to pipe-src-volume-capture.m4
since it contains a volume component. A new macro pipe-src-capture.m4
is created to provide pipeline building block without volume.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
The earlier error message was hard to understand and could be
mistaken as internal fail. A redundant trace message about block
sizes is removed because the block sizes are set in each copy()
in current SRC version.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
This patch avoids wrong configuration for PCM format and audio
corruption in capture pipelines usage if the pipeline requires
format conversion.
Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
Now rt711 is in SDW mode and rt1308 is in I2S mode on TGL RVP
Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
When new pipeline is created we need to also verify whether
given pipeline id is already taken.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Renames PLATFORM_HOST_DMA_TIMEOUT to HDA_DMA_TIMEOUT and
moves to hda-dma, where it belongs.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
Renames PLATFORM_HOST_DMA_MASK to PLATFORM_DW_DMA_HOST_MASK
and moves to dw-dma header, where it belongs.
Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
In case of unsuccessful scheduler task init, the pipeline
task init should also fail.
Signed-off-by: Janusz Jankowski <janusz.jankowski@linux.intel.com>
Tomasz Lauda