Commit Graph

3995 Commits

Author SHA1 Message Date
Jaska Uimonen db7671acba topology: sof-hsw-rt5640.m4: remove topology
Remove as unsupported platform.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 0153022712 topology: sof-bdw-codec.m4: add scheduling dai to media pipe
Media pipe is missing the scheduling component, so move it after the dai
definition and add the scheduling component.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 8d62caef00 topology: sof-cml-rt5682.m4: remove extra parameters
sof-cml-rt5682 dmic definition has some extra parameters that should be
removed.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen aa007bbd84 topology: sof-imx8qxp-wm8960.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 254b3a8db0 topology: sof-imx8qxp-nocodec.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen f14ddac377 topology: sof-imx8qxp-nocodec-sai.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen b992b7c69f topology: sof-imx8qxp-cs42888.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen c1fb77a653 topology: sof-cht-src-50khz-pcm512x.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen cc6ab45e85 topology: sof-cht-max98090.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 5a0f44a65a topology: sof-byt-codec.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD and pipeline.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 6e1ddddd8d topology: sof-cht-rt5682.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen f38a07615b topology: sof-cht-nocodec.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD and pipeline.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen 92f326e1df topology: sof-bdw-codec.m4: add time domain DMA
Add time domain DMA explicitly to DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Jaska Uimonen fc9acc9d94 topology: intel-generic-dmic.m4: fix dai parameters
Fix errorneous parameters in DAI_ADD.

Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-11-25 16:12:14 +00:00
Marcin Maka d6fe2b138b pm: cavs: fix literal dcache lock in power down
Compiler options has to be changed in order to compute
the literal block address correctly.

Some literals must be declared explicitly and loaded
indirectly to make sure that compiler does not optimize
the out to another shared region.

Signed-off-by: Marcin Maka <marcin.maka@linux.intel.com>
2019-11-22 20:42:10 +00:00
Paul Olaru 100621d422 platform: imx8: Remove all references to SSP clock
The i.MX8 platform doesn't have an SSP clock. We had a fake define for
this platform due to prior inflexibility in SOF itself. Now that said
lack of flexibility is gone, this patch removes all such references.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-22 18:32:33 +00:00
Paul Olaru ee9283c159 sof: lib: notifier: Do not break build on platforms without CLK_SSP
Some platforms do not have a SSP clock, so a dummy define for CLK_SSP
and related macros shouldn't be required to exist in order for the
firmware to build.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-22 18:32:33 +00:00
Karol Trzcinski fcf6c8c416 trace: Use uncached memory in trace_point and panic
It didn't work correctly if multiple cores write to "sw regs"
 allocated on the same cache line.

Signed-off-by: Karol Trzcinski <karolx.trzcinski@linux.intel.com>
2019-11-22 14:16:33 +00:00
Tomasz Lauda b2f088789d dw-dma: enable channel linear link position
Enables DW-DMA channel linear link position counter based
on the selected peripheral connection. It can be used
to retrieve timestamping information on platforms supporting it.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-22 14:09:16 +00:00
Tomasz Lauda d343039093 shim: cleanup and extend GPDMA shim registers
Cleanups definitions of GPDMA shim registers for all cAVS platforms
and extends them by adding support for channel linear link position
control register.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-22 14:09:16 +00:00
Karol Trzcinski 714859d925 trace: use trace_point instead of platform_* in boot_loader.c
After disabling tracing code have compilation error because of
implicit declaration of platform_trace_point function.
After calling through trace_point it is replaced with empty
define after disabling trace.

Signed-off-by: Karol Trzcinski <karolx.trzcinski@linux.intel.com>
2019-11-22 09:45:58 +00:00
Paul Olaru 9b5dc8c6ef sof: Align interrupt stacks
Xtensa ABI requires the stack to always be aligned to a multiple of 16
bytes. This commit aligns the stacks used for interrupt handling.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-21 16:45:33 +02:00
Janusz Jankowski a25d50eb64 clk: platform agnostic clocks
Create abstract interface for clocks and move platform specific
clocks code to platform folders.
It was also necessary to move SSP clocks declarations to
SSP driver code to decouple clocks logic from mandatory
SSP clocks.

Signed-off-by: Janusz Jankowski <janusz.jankowski@linux.intel.com>
2019-11-21 14:38:28 +00:00
Lech Betlej 07444f4b78 Remove doxygen warnings during documentation generation
The changes fix command unbalanced groupings and remove discrepancy
between parameters in function declaration & definition of
set_power_gate_for_memory_address_range() function.

Signed-off-by: Lech Betlej <lech.betlej@linux.intel.com>
2019-11-21 14:34:26 +00:00
Paul Olaru 0e1efdfaad platform: imx: Enable WAITI_DELAY
The description says that any LX6 Xtensa architecture revision DSP
should have this enabled, and the particular DSP in the i.MX8 does fit
this description.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-20 10:47:09 +00:00
Paul Olaru 75a6a8cce3 platform: imx: Update build script for compiling with XCC
The tools version and core must be correctly defined in order to be
able to compile for this platform.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-20 10:45:47 +00:00
Slawomir Blauciak c7b914dd14 ipc: channel map structures and api
This change adds stream map and channel map structures
used for channel re-routing and stream aggregation.

Signed-off-by: Slawomir Blauciak <slawomir.blauciak@linux.intel.com>
2019-11-20 10:44:51 +00:00
Tomasz Lauda 63a552992c topology: revert media pipes to 4000 scheduling period
Reverts all changed media pipelines to again have 4000 ms
scheduling period. Change was introduced in order to workaround
firmware scheduling limitation, but with pipelines scheduled
separately we can revert it back.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda e3ba648de0 pipeline: schedule pipelines separately
This patch enables separate scheduling of connected
pipelines. It allows for different scheduling periods
between connected pipelines and flexible controlling
of such topologies.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 6de576c9d7 topology: fix connected pipelines' priorities
Fixes pipelines' priorities in multipipe topologies.
The highest priority is 0.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda f42ddc06fd ll_schedule_domain: use pipeline_task in DMA domains
Uses pipeline_task in DMA domains to check, if tasks should be even
registered on interrupts. Non registrable tasks are the one,
whose pipelines are not the owners of scheduling component e.g.
host pipelines connected to mixer pipeline. Such tasks are still
added to the scheduler's list and executed, but they are driven
by the pipelines with scheduling component.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 5ead758e24 pipeline: use pipeline_task
Initializes and uses pipeline_task instead of regular task.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 3de6844497 task: add pipeline_task
Adds definition of pipeline_task. It's a task type registered
by pipelines and used in DMA scheduling domains.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 5dca048ed6 schedule: remove SOF_SCHEDULE_FLAG_SYNC/ASYNC flags
Removes SOF_SCHEDULE_FLAG_SYNC and SOF_SCHEDULE_FLAG_ASYNC.
They are no longer used nor needed.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 6ffcd61c19 ll_schedule: use domain property instead of sync/async flags
Changes ll scheduler implementation to use synchronous property
of domain to check if given task should be scheduled synchronously
or asynchronously. It makes sense, since it's heavily dependent
on particular domain functionality.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda 95ba01ebd2 ll_schedule_domain: add synchronous field
Adds new synchronous field to indicate if tasks registered
to this domain should be scheduled synchronously or asynchronously.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda d9aecd8498 ll_schedule_domain: describe structure
Describes ll_schedule_domain structure.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda b734091d63 ll_schedule_domain: pass task during unregistration
Changes domain_unregister operation to also receive task
being unregistered.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Tomasz Lauda cb5506f0b9 pipeline: cleanup header file
Removes unused pipeline_schedule() declaration and
not needed inclusion of task header.

Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-11-19 10:56:15 +00:00
Paul Olaru 1613f10689 drivers: imx: interrupt: Change how the cascade IRQ template is defined
Instead of taking the name from an array of strings (which is allowed by
GCC) I compose the name directly inside the IRQSTR_CASCADE_TMPL_DECL
macro. GCC is able to detect that the name is a compile time constant
and allows the old code, XCC does not and requires this change.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-19 11:15:16 +02:00
Paul Olaru aee8e0553a drivers: imx: edma: Make soff and doff signed
This allows the SGN macro to no longer generate a warning on the "-1"
case and thus allows building with XCC. GCC doesn't seem to care about
this one. No actual change in the logic itself.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-19 11:15:16 +02:00
Guido Roncarolo dbb70c840c imx: topology: Add capture pipeline for the wm8960 codec case
Signed-off-by: Guido Roncarolo <guido.roncarolo@nxp.com>
2019-11-18 15:55:18 +00:00
Paul Olaru 67ce20a5c2 imx: topology: Add capture pipeline for the CS42888 codec case
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru aa293bbe21 drivers: imx: esai: Remove PADC bit from rx configuration
PADC means to have ESAI pad samples with zeros instead of sign-extending
them when they are smaller than the (32-bit) container. This doesn't
make senseon capture and indeed that specific bit is hardware reserved.
So don't use it.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru 205b079253 drivers: imx: esai: Various cleanups
Generally comment cleanups but also moving the "|" operator to be at
the end so that the various options in dai_update_bits are aligned.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru d28278808a drivers: imx: esai: Set configurations for capture
The configurations will be mostly similar to those used for playback,
but while the ESAI is master on playback it must be slave on capture
as a workaround due to hardware limitations. These differences must be
hardcoded due to the topology not specifying these configurations for
each direction of the link.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru e17aa44c30 drivers: imx: edma: Correctly compute available data size on capture
Currently this just returned a zero and wasn't able to correctly
interpret the direction of the channel.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru ea6060c9ca drivers: imx: edma: Store direction from config into the channel data
This direction is to be used later.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Paul Olaru fa6206d47c platform: imx: dai: Get the direction from the component instead of the IPC
The direction was already configured correctly in the component during
dai_new, and the IPC data is shared for both instances of the DAI
component (playback and capture).

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2019-11-18 11:06:06 +00:00
Bartosz Kokoszko 655d077f72 spinlock: spin_try_lock refinement
Use block expression instead of do {} while(0) macro
in spin_try_lock in order to return its value in a
safer way.

Signed-off-by: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
2019-11-15 14:17:01 +00:00