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cavs: deduplicate power down sequence for cavs platforms 

cAVS power down sequence refactored by moving CannonLake (cAVS 1.8)
implementation to cavs lib as a base for cAVS 1.8/2.0/2.5 common
code. ApolloLake (cAVS 1.5) specific implementation remains as a
platform specific code.

Signed-off-by: Lech Betlej <lech.betlej@linux.intel.com>
This commit is contained in:
Lech Betlej 2019-10-03 15:46:54 +02:00 committed by Tomasz Lauda
parent 6d3d5bcdad
commit c548489e38
14 changed files with 64 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/platform/apollolake/CMakeLists.txt
View File

@ -2,8 +2,6 @@
add_subdirectory(lib)
add_local_sources(sof power_down.S)
add_executable(boot_module boot_module.c)
add_executable(base_module base_module.c)

20
src/platform/apollolake/include/platform/lib/asm_ldo_management.h Normal file
View File

@ -0,0 +1,20 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2019 Intel Corporation. All rights reserved.
*
* Author: Lech Betlej <lech.betlej@linux.intel.com>
*/
/**
* \file platform/apollolake/lib/asm_ldo_management.h
* \brief Macros for controlling LDO state specific for cAVS 1.5. The header is
* intended to be used in Apollolake specific implementation of power_down
* routine
*/
#ifndef __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__
#define __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__
#include <cavs/lib/asm_ldo_management.h>
#endif /* __PLATFORM_LIB_ASM_LDO_MANAGEMENT_H__ */

8
src/platform/apollolake/include/platform/asm_memory_management.h → src/platform/apollolake/include/platform/lib/asm_memory_management.h
View File

@ -6,13 +6,13 @@
*/
/**
* \file platform/apollolake/include/platform/asm_memory_management.h
* \file platform/apollolake/include/platform/lib/asm_memory_management.h
* \brief Macros for power gating memory banks specific for Apollolake
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#ifndef __PLATFORM_ASM_MEMORY_MANAGEMENT_H__
#define __PLATFORM_ASM_MEMORY_MANAGEMENT_H__
#ifndef __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__
#define __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__
#ifndef ASSEMBLY
#warning "ASSEMBLY macro not defined."
@ -67,4 +67,4 @@
bne \ax, \ay, 1b
.endm
#endif /* __PLATFORM_ASM_MEMORY_MANAGEMENT_H__ */
#endif /* __PLATFORM_LIB_ASM_MEMORY_MANAGEMENT_H__ */

4
src/platform/apollolake/lib/CMakeLists.txt
View File

@ -1,3 +1,5 @@
# SPDX-License-Identifier: BSD-3-Clause
add_local_sources(sof clk.c)
add_local_sources(sof
clk.c
power_down.S)

7
src/platform/apollolake/power_down.S → src/platform/apollolake/lib/power_down.S
View File

@ -6,13 +6,12 @@
*/
/**
* \file platform/apollolake/power_down.S
* \file platform/apollolake/lib/power_down.S
* \brief Power gating memory banks - implementation specific for Apollolake
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#include <platform/asm_ldo_management.h>
#include <platform/asm_memory_management.h>
#include <platform/lib/asm_ldo_management.h>
#include <platform/lib/asm_memory_management.h>
#include <sof/lib/memory.h>
#include <sof/lib/shim.h>

2
src/platform/cannonlake/CMakeLists.txt
View File

@ -2,8 +2,6 @@
add_subdirectory(lib)
add_local_sources(sof power_down.S)
add_executable(boot_module boot_module.c)
add_executable(base_module base_module.c)

109
src/platform/cannonlake/include/platform/asm_ldo_management.h
View File

@ -1,109 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2018 Intel Corporation. All rights reserved.
*
* Author: Lech Betlej <lech.betlej@linux.intel.com>
*/
/**
* \file platform/apollolake/include/platform/asm_ldo_management.h
* \brief Macros for controlling LDO state specific for cAVS 1.5
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#ifndef __PLATFORM_ASM_LDO_MANAGEMENT_H__
#define __PLATFORM_ASM_LDO_MANAGEMENT_H__
#ifndef ASSEMBLY
#warning "Header can only be used by assembly sources."
#endif
#include <sof/lib/shim.h>
.macro m_cavs_set_ldo_state state, ax
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
s32i \state, \ax, 0
memw
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
.endm
.macro m_cavs_set_hpldo_state state, ax, ay
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
and \ay, \ax, \ay
or \state, \ay, \state
m_cavs_set_ldo_state \state, \ax
.endm
.macro m_cavs_set_lpldo_state state, ax, ay
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0
// LP SRAM mask
movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
and \ay, \ax, \ay
or \state, \ay, \state
m_cavs_set_ldo_state \state, \ax
.endm
.macro m_cavs_set_ldo_on_state ax, ay, az
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \ax, \az
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
or \ax, \az, \ax
m_cavs_set_ldo_state \ax, \ay
.endm
.macro m_cavs_set_ldo_off_state ax, ay, az
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
or \ax, \ax, \az
s32i \ax, \ay, 0
l32i \ax, \ay, 0
.endm
.macro m_cavs_set_ldo_bypass_state ax, ay, az
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
or \ax, \ax, \az
s32i \ax, \ay, 0
l32i \ax, \ay, 0
.endm
#endif /* __PLATFORM_ASM_LDO_MANAGEMENT_H__ */

3
src/platform/icelake/include/platform/lib/shim.h
View File

@ -146,6 +146,9 @@
#define HSRMCTL0 0x71D14
#define HSPGISTS0 0x71D18
#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
#define HSPGCTL1 0x71D20
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28

8
src/platform/apollolake/include/platform/asm_ldo_management.h → src/platform/intel/cavs/include/cavs/lib/asm_ldo_management.h
View File

@ -7,12 +7,12 @@
/**
* \file platform/apollolake/include/platform/asm_ldo_management.h
* \brief Macros for controlling LDO state specific for cAVS 1.5
* \brief Macros for controlling LDO state specific for cAVS
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#ifndef __PLATFORM_ASM_LDO_MANAGEMENT_H__
#define __PLATFORM_ASM_LDO_MANAGEMENT_H__
#ifndef __CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#define __CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#ifndef ASSEMBLY
#warning "Header can only be used by assembly sources."
@ -106,4 +106,4 @@ s32i \ax, \ay, 0
l32i \ax, \ay, 0
.endm
#endif /* __PLATFORM_ASM_LDO_MANAGEMENT_H__ */
#endif /* __CAVS_LIB_ASM_LDO_MANAGEMENT_H__ */

18
src/platform/cannonlake/include/platform/asm_memory_management.h → src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h
View File

@ -8,24 +8,25 @@
/**
* \file platform/cannonlake/include/platform/asm_memory_management.h
* \brief Macros for power gating memory banks specific for cAVS 1.8
* \(CannonLake)
* \(CannonLake) and cAVS 2.0 (IceLake)
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#ifndef __PLATFORM_ASM_MEMORY_MANAGEMENT_H__
#define __PLATFORM_ASM_MEMORY_MANAGEMENT_H__
#ifndef __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
#define __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
#ifndef ASSEMBLY
#warning "ASSEMBLY macro not defined. Header can't be inluded in C files"
#warning "The file is intended to be includded in assembly files only."
#warning "ASSEMBLY macro not defined. Header can't be included in C files"
#warning "The file is intended to be included in assembly files only."
#endif
#include <sof/lib/memory.h>
#include <sof/lib/shim.h>
#if CAVS_VERSION >= CAVS_VERSION_1_8
/**
* powers down entire hpsram. on entry lirerals and code for section from
* where this code is executed needs to be placed in memory which is not
* Macro powers down entire HPSRAM. On entry literals and code for section from
* where this code is executed need to be placed in memory which is not
* HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or
* L1 SRAM)
*/
@ -75,4 +76,5 @@
bnez \ax, 1b
.endm
#endif /* __PLATFORM_ASM_MEMORY_MANAGEMENT_H__ */
#endif /* CAVS_VERSION == CAVS_VERSION_1_8 */
#endif /* __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ */

1
src/platform/intel/cavs/lib/CMakeLists.txt
View File

@ -6,4 +6,5 @@ add_local_sources(sof
memory.c
pm_runtime.c
pm_memory.c
power_down.S
)

16
src/platform/cannonlake/power_down.S → src/platform/intel/cavs/lib/power_down.S
View File

@ -6,17 +6,21 @@
*/
/**
* \file platform/cannonlake/power_down.S
* \brief Power gating memory banks - implementation specific for platfroms
* \file platform/intel/cavs/lib/power_down.S
* \brief Power gating memory banks - implementation specific for platforms
* with cAVS 1.8 (i.e. CannonLake) and cAVS 2.0 (i.e. IceLake)
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#include <platform/asm_ldo_management.h>
#include <platform/asm_memory_management.h>
#include <cavs/version.h>
#include <cavs/lib/asm_ldo_management.h>
#include <cavs/lib/asm_memory_management.h>
#include <sof/lib/memory.h>
#include <sof/lib/shim.h>
#if CAVS_VERSION >= CAVS_VERSION_1_8
.section .text, "ax"
.align 64
literals:
@ -42,7 +46,6 @@ literals:
#define temp_reg3 a9
#define pfl_reg a15
power_down:
entry sp, 32
// effectively executes:
@ -75,7 +78,7 @@ _PD_DISABLE_LPSRAM:
_PD_DISABLE_HPSRAM:
/* if value in memory pointed by pu32_hpsram_mask = 0
(hpsram_pwrgating_mask) - do not disable hpsram. */
beqz pu32_hpsram_mask, _PD_SEND_IPC
beqz pu32_hpsram_mask, _PD_SEND_IPC
/* mandatory sequence for LDO ON - effectively executes:
* m_cavs_s_set_ldo_hpsram_on_state();
@ -156,4 +159,5 @@ loop:
.size power_down , . - power_down
#endif /* CAVS_VERSION >= CAVS_VERSION_1_8 */

3
src/platform/suecreek/include/platform/lib/shim.h
View File

@ -150,6 +150,9 @@
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28
#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58

3
src/platform/tigerlake/include/platform/lib/shim.h
View File

@ -159,6 +159,9 @@
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28
#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x))
#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x))
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58