- Updated GPIO table to match BIOS PV ER3 release.
- Disable SCI for D13 and E00.
- Process the GPIO table from dlt file instead
of the hard-coded table. The mGpioTablePostMemAdlPsDdr5Rvp
is only for reference purposes.
- Move DEBUG CODE END to later part of the GPIO function in
order to add GPIO prints when required.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixes the KW issue that is reported due to NULL
pointer deference. Moved up the code where CfgData checks for NULL.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch fixed BDF for UFS device, bus number and function
number are improperly ported and this patch fixed the issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the hang seen during a reboot cmd on ADLS DDR4 board.
Setting the DmiMaxLinkSpeed to Auto mode.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
HsPhy feature is only applicable for ADLS and not for others.
Adding a condition to apply only for it.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
This patch added support to get csme boot time performance
data and display it in perf command and also before booting
to linux.
Introduced a board config option BOOT_PERFORMANCE_MASK to control
PcdBootPerformanceMask, BIT 2 now enables printing CSME boot
performance data.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Sync from EHL BIOS.
Error: ACPI BIOS Error (bug): AE_AML_BUFFER_LIMIT, Field [IOF2] at
bit offset/length 712/16 exceeds size of target Buffer (664 bits)
Signed-off-by: Randy Lin <randy.lin@intel.com>
Update FSP UPDs and VBT changes as part of the ADLP MR release.
TEST=Tested to boot to OS.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
*Adds code to support the updating
of ACM FW via capsule
*Adds code that disallows for the
roll back of ACM FW
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
This patch can reduce the chance of setting SBL_SOURCE when the
SBL root directory is not named as "SblOpen" or when the scripts
are run from the path other than the SBL root directory. Also note
that os.path.abspath() returns the absolute path relative to the
current working directory instead of the real path of __file__.
So in StitchIfwi.py, sblopen_dir was incorrect since the working
directory had been changed before calling stitch().
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
FSPT doesn't allow to enable full flash code cache.
Bootloader configures MTRR in non BTG cases to avoid
performance penalty.
This fixes the ADL boot from BP1 partition.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
PSE is enabled by default.
During SBL building, it will check the existance of PSE FW binary.
If it is missing in binaries folder, the PSEF won't be appended in
container list and casue StitchIFWI script fail if it try to update.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Also set the CpuTempSensorReadEnable = 1
It was renamed from PchCpuTempSensorEnable
and removed in commit 44faa431c9
Signed-off-by: Randy Lin <randy.lin@intel.com>
The default FSP UPD value for Lp5BankMode doesn't work
for all the platforms. It would help override it using
SBL configuration data if it is exposed.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch added changes required for ADLN FSP Sync and
also did the following
1) Added SA config for DDR5 CRB
2) Initialized VBT to enable 2 HDMI and a DP port
3) Moved FSPM config to delta file
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This reverts commit 1caacefeb5.
The USB port that does not respond to USB bus enumeration is port 8 on
the newer UPX board. The old UPX board might have different behavior.
The original commit was valid on old UPX board only, and this patch
reverted it. Confirmed the USB error message disappeared on the new
UPX board after the reverting.
Signed-off-by: Maurice Ma <mauricemx.ma@gmail.com>
Only enabled IehMode when IBECC error injection is disabled
Iehmode will cause failure in IBECC error injection test
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Match the FSP include path from Board Config to that of
FspBin inf file so it fixes the build issue.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
By default OsLoader payload shell is only available in debug build.
In some case customer also wants to have shell in release build.
So add a BootToShell configuration item to enable shell in release build.
By default BootToShell is set to 0. When it is set to 1 the shell behavior
would be same in release and debug build.
NOTE: user could add this line in platform dlt file to set BootToShell.
GEN_CFG_DATA.BootToShell |1
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch assigns Timed GPIO Cfg Data to the NVS variables
in order for the OS to load this driver.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
* Generate platform build name definition
Same code could be shared by different platforms. At same time,
some platform might need do minor change to the shared code.
In order to support this case, this patch updated the build tool
to generate a macro definition for current build platform name
in a header file. so the shared code could have platform specific
code change with this macro definition.
e.g. add "#define #define PLATFORM_ADLS 1" for ADLS.
Signed-off-by: Guo Dong <guo.dong@intel.com>
* [ADLS] update
FspsUpdUpdateLib could be shared by different platform,
use ADLS macro definition instead of PcdAdlLpSupport for
ADLS specific change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
SBL uses PcdMemoryMapEntryNumber to control the max entry
number of memory map info HOB. In some platforms, CML
encountered "Memory map failure" due to the actual entry
number exceeding it. So increase the max to accommodate
the case.
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This patch fixed build issues caused by adding L2QosEnumerationEn UPD
which is not present on other ADL platforms.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
The default big core number was set to 8, it has to be overridden if
the CPU number is not 8. Had better set to 0xFF to all active big cores.
Also it mentioned the default value is 0xFF in the help message.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Unlike ADLS, TSN link speed will be coming from the Cfg data.
New TSN GPIO table needed for ADLN board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Previous commit fe6cf3272 unexpectedly changed the AUTO payload-switching
behavior. This patch restores the behavior to the original design.
Verified: TGL-UP3 RVP
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Add PchPseAicEnabled and PchUnlockGpioPads in
CfgData_Silicon.yaml file to allow modification
using Config Editor tool.
Signed-off-by: jinjhuli <jin.jhu.lim@intel.com>
Some of the RTCT table entries werent populated due to this
missing UPD setting. Hence, assigning it to the correct value.
TEST= Verified the fix on ADLS board.
Signed-off-by: Sindhura Grandhi <sindhura.grandhi@intel.com>
Kalp Parikh