This commit resolves the issue where the SMI handler was not being triggered
during S3 resume. The problem was due to the functions RestoreS3RegInfo and
TriggerPayloadSwSmi not being called.
In addition, the commit also:
1. unset the PME_B0_EN as UEFI Payload does not have its handler
2. remove the ClearSmbuStatus() because
- the HSTS.B_SMBUS_IO_SMBALERT_STS in SMBUS (B0:D31:F4) should be
handled and cleared by device driver or an appropriate SMI handler.
- the ClearSmi() will clear GPE0_STS_127_96.SMB_WAK_STS if it is set
3. unset (FSPS) PeiGraphicsPeimInit and GraphicsConfigPtr during S3 resume
4. narrow the var scope of mSmmBaseInfo and mS3SaveReg
5. add required bitfield declaration
Verified with:
1. UEFI Payload + Ubuntu on EHL CRB (release build)
2. OSLoader (release build)
when FEATURES_CFG_DATA.Features.S0ix = 0
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
The patch handles EfiResetShutdown. With the patch, one can
test "reset off" under OS Loader.
The patch also
- fixes a wrong reference error in ResetSystemLib.inf.
- add shutdown text in CmdReset.c
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
* fix: [Common] FwVendor/OemId Array compared against 0
Since it is an array the test evaluates as true and the check is
unnecessary.(CWE-398)
UINT8 FwVendor[EFI_ACPI_PSD_FW_VENDOR_SIZE];
UINT8 OemId[6];
Signed-off-by: Randy <randy.lin@intel.com>
* fix: [Common] Unchecked return value for HeciGetMeMode
If the function returns an error value, the error value
may be mistaken for a normal value.
In HeciSend: Value returned from a function is
not checked for errors before being used. (CWE-252)
Signed-off-by: Randy <randy.lin@intel.com>
---------
Signed-off-by: Randy <randy.lin@intel.com>
EHL FSP does not send EOP (End Of Post) message at the
Ready to Boot. The patch adds support for SBL to send
the EOP during Ready to Boot.
Verified: EHL CRB
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
- update FSP version to MR5 FSP (09.04.30.51)
- update microcode version to 17
- update platform version to 1.5
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Resolve the build break when remove the O1b2 CC flag.
error LNK2001: unresolved external symbol __allshl
Signed-off-by: Randy Lin <randy.lin@intel.com>
Signed-off-by: Randy Lin <randy.lin@intel.com>
The HPET timer address is wrong at first time invoke.
Assign to fixed value directly.
Verified on EHL TGLU.
Signed-off-by: Randy Lin <randy.lin@intel.com>
- update FSP version to MR4 FSP (09.04.25.11)
- update VBT version to MR4 FSP (244)
- update microcode version to 16
- update EHL platform version to 1.4
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
EHL DMA controllers are hidden at PSF level in reference code,
DMA controllers are reported as ACPI devices if ownership is Host.
So should not check DMA PCI header for DSDT table patching.
Update the change follow EHL reference code.
Signed-off-by: Gavin Xue <gavin.xue@intel.com>
Found PSDS ACPI table reporting incorrect value
and fixing by referring the BIOS method to retrieve
right value. Also Enable Platform Security Discovery.
Verify on CRB platform.
Signed-off-by: Randy Lin <randy.lin@intel.com>
Also set the CpuTempSensorReadEnable = 1
It was renamed from PchCpuTempSensorEnable
and removed in commit 44faa431c9
Signed-off-by: Randy Lin <randy.lin@intel.com>
Remove FSP headers due to the FSP download script
will check if FSP header exist. It will only replace
if there is no existing FSP headers.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch added additional files to be excluded from patch check.
For example, txt, ini, app, common, template, rule, Makefile,
GNUmakefile, etc.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch added payload selection GPIO configuration
hardcoded GPIO pin for payload selection.
It also fixed#1196.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Co-authored-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For consistency and public understanding, rework to change
'LowPowerS0Idle' to 'S0ix'.
- rename LowPowerS0Idle to S0ix
- add s0ix variable in PlatformData.h
- add s0ix flag check in stage 1B
- move Tcc s0ix support flag from stage 2 to stage 1B
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
There is a discrepancy between how Linux reads GPIO
and how bootloader is presenting it. This causes Linux
distros to crash, even in the installer,unless a kernel
module parameter has been passed:
'module_blacklist=pinctrl_elkhartlake'
The customer, Red Hat, is using RHEL 8 4.18.0-315.
There appears to be a discrepancy between how Linux reads GPIO and how
the Intel BIOS is presenting it.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Add latest Intel® Time Coordinated Computing support for EHL.
Here are the changes:
- Update the TCC subregion layout
- Use the common TCC config data
- Use the common TCC library for RTCT table
- Support TCC DSO cfg, Cache cfg and CRL binaries loading
- Rename TCC variable to follow TCC V2 naming
- Increase the stage 2 size from 0x89000 to 0x91000 to accommodate
the new changes
- Add latest FspmUpd and FspsUpd header files for TCC v2 support
(will be removed once FSP github updated the latest EHL FSP package)
- Change default boot options for RTCM support
TCC mode is turned off by default.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
Use the newly added PchSbiAccessLib in common package,
for all the current platfroms. Platform specific PchSbi Lib
is removed.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Issue seen in Yocto RT kernel that PSE GBE0 Transmission.
Found out that GPPC_A_5.pmode=0 (RGMII0_TXCTL) which expected
to be 0x1.
override become 0x0.
After investigation these PADCFGLOCK_GPP_A_0 and PADCFGLOCKTX_GPP_A_0
registers should be 0xFFFFFF to lock the GPIO GPPC_A_x to prevent
modificaiton to the GPIO.
Implemented GpioLock function in GpioLib.c to fix this issue.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This CL fixes the long time issue where EHL SBL failed to init
properly and solely relies on FSP to handle the UART unit, and
hence the limitation of Hidden Mode UART only, as we observed
the UART output gone missing after PCI enumeration if we set
respective UART port into PCI mode in FSP. By hiding the UART,
OS will not be able to see the UART device as PCI device and
lose control to the UART device.
Due to hardware design, different uart could use different
LPSS_IO_MEM_PCP register offset for UART clock setup.
This CL includes dynamic configuration for clock setup by
reading the size of UART control register. Since this is pretty
generic for most of platforms, will plan to move more UART codes
to common codes in the future.
Second fix changes the default UART mode for both FSP-T and FSP-S
to skip uart init, and let SBL solely handles it and setup as a
PCI device.
Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
EHL, TGL supports multiple OEM keys and their revocation
by CSE. This patch supports,
- CMDI interface to perform key revocation using
OEMKEYREVOCATION string in cmd file.
- EHL HECI APIs for OemkeyRevoke and to get key status
- FW componets are sorted as per required order.
CSME and BIOS should be signed with new keys and
both components would go together with capsule update.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Resolved yocto hang issue after booted into OS
for non Fusa sku.
Enabled s0ix for yocto and windows.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
skasim