Current MTRR lib assumes the MTRR number is always 10. Instead,
this patch follows the IA manual to get the actual MTRR number
through MTRR capability register.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SPI clock source was on and gating s0ix entry, due to linux OS could
trigger SPI Write Protection Disable bit and hence set the SPI
Synchronous SMI Status bit. This CL fixes it by clearing the SPI
Synchronous SMI Status bit prior to S0ix entry.
Traditionally, it is expected for bootloader to clear this bit in
SMI handler upon S0ix entry, due to SBL being free of SMI, clearing
this bit from ACPI table has the same effect.
Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
As reported in issue #1055, when "--enable-kvm" flag is enabled
within QEMU, SBL does not boot. It is because KVM does not allow
certain MSR access. This patch removed NO_EVICTION_MODE MSR access
from QEMU FSP TempRamInit. By doing so, it allows QEMU to boot
with KVM enabled.
It fixed#1055.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
TGL supports multiple OEM keys and their revocation
by CSE. This patch supports HECI APIs for OemkeyRevoke
and to get key status. This is port from TGLH platform
implemetation.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch adapts common btg utility and restructures
stitch script and separates security functionality.
BtgSign.py - Common Boot guard signing and oem key manifest generation.
It also supports signing in standalone mode. Stanalone mode can
be used sign bootloader bin and stitch using FIT tool.
security_stitch_help.py - Interface functionality for Btg manifest and
update xml with security updates. This is as per the client
platform FIT xml format.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This CL fixes the long time issue where EHL SBL failed to init
properly and solely relies on FSP to handle the UART unit, and
hence the limitation of Hidden Mode UART only, as we observed
the UART output gone missing after PCI enumeration if we set
respective UART port into PCI mode in FSP. By hiding the UART,
OS will not be able to see the UART device as PCI device and
lose control to the UART device.
Due to hardware design, different uart could use different
LPSS_IO_MEM_PCP register offset for UART clock setup.
This CL includes dynamic configuration for clock setup by
reading the size of UART control register. Since this is pretty
generic for most of platforms, will plan to move more UART codes
to common codes in the future.
Second fix changes the default UART mode for both FSP-T and FSP-S
to skip uart init, and let SBL solely handles it and setup as a
PCI device.
Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
SMIE is checked in Tpm asl before SMI is triggered.
Removal of this definition causes physical presence
usecases failure.
TEST=Verified TPM clear usecases with windows boots
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Current APL SBL code will enable IA_UNTRUSTED mode only at end of
firmware notification. It might be too late for certain conditions.
This patch moves it to be set at end of stage in SBL. In this way,
it ensures the bit is set before launching any external payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch removed next line character printed during
progress update of csme firmware update, this would remove
lot of prints in the next line and show progress much more
user friendly.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
EHL, TGL supports multiple OEM keys and their revocation
by CSE. This patch supports,
- CMDI interface to perform key revocation using
OEMKEYREVOCATION string in cmd file.
- EHL HECI APIs for OemkeyRevoke and to get key status
- FW componets are sorted as per required order.
CSME and BIOS should be signed with new keys and
both components would go together with capsule update.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
Current PCI Enum Lib scopes for only Apperture resources
for a PPB. But some OSes (like ESXi) expect BAR0 & BAR1
(Offset 0x10/0x14) to be allocated resources accordingly.
Otherwise, PPB enumeration doesnt happen correctly and
devices behind PPB are not registered at all.
This patch adds the functionality to assign valid resources
to BAR0(0x10) and BAR1(0x14) for a PPB also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch fixed an error that occur during updating a
binary that is not aligned to 4k. Current code will always
update next 4K block. This patch adjusted the block length
to remaining size other than 4K.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch fixes the multiple build issues which are observed
when ENABLE_SOURCE_DEBUG config is set to 1.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
This patch added FSP swapping script to support replace a FSP
binary inside SBL IFWI or BIOS image.
To use it, use
python BootloaderCorePkg\Tools\FspSwap.py ifwi.bin fsp.bin
The default output directory is "Out".
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
CsmePciReadBuffer function prototype is alligned as
per the CSME fwupdate lib. It fixes issue with
CSME capsule fw update.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This Patch did the following
- TsegSize config options is defined in CfgData_Memory.yaml.
- with 64GB RAM, slow boot issue was reported on ubuntu_20.0.
Root cuase of the issue is due out of MTTR's and unable to cover
portion of higher memory ranges. this patch fixes this issue.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
It was reported that some platform had MP waking up issue after
switching to using X2APIC library. By comparing the library, found
X2APIC removed 2nd IPI sending in the flow. This 2nd IPI is
required per IA specification. The patch added it back.
Tests have been done and confirmed it fixed the issues seen on
thos platforms.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
ACPI package has been upgraded to acpica-tools_20200925-1.2_amd64
in order to fix the build issue. The old ACPICA tool URL is not
valid anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch removed duplicated X2APIC enabling code. Instead, it
enables X2APIC in a common function. By doing so, the very first
waking up will be done in APIC mode. Afterwards, it will be using
X2APIC mode if enabled by PCD.
This patch also fixed an X2APIC ACPI MADT issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Linux reported incorrect MTRR mask programming in SBL. This patch
fixed this issue by using the proper MTRR mask for GFX FB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Currently, the 1st time stamp includes FSP-T execution time in X64.
This will read the 1st time stamp before TempRamInit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added X2APIC support. It is to enable the case when
APIC ID is greater than 255. This patch only handle core wakeup
portion. Platform still needs to handle ACPI related changes for
X2APIC.
X2APIC lib is backward compatible with XAPIC lib. So there is no
need to use XAPIC lib anymore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Certain platforms can't support GpioLockUnlock, so let
them return the Opcode they want to use for locking.
Also updated dependent platform.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
The ApDataPtr->CProcedure was wrongly updated in previous patch.
This patch fixed it and CPU task name from CProcedure to TaskFunc
to avoid confusion.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch changed QEMU FSP to use INF file to provide commit id.
It also synced up to the latest EDK2 stable tag edk2-stable202011.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Resolved yocto hang issue after booted into OS
for non Fusa sku.
Enabled s0ix for yocto and windows.
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
This patch adds support to build CSME firmware update driver.
BUILD_CSME_UPDATE_DRIVER in BoardConfig.py must set 1 to build csme FWU
driver.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
There is request to utilize MP in OsLoader. To support it, it is
desired to delay MP init done signal to the end of the OsLoader.
This patch moved the MP init done signal into board ReadyToBoot
notification so that MP is still alive in OsLoader phase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In some cases Bootloader will build GFX HOB. This patch updated
SBL to check the bootloader GFX HOB first before building a new
GFX HOB from FSP. This is to avoid duplicated GFX HOB to be
generated in bootloader HOB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed a failure in firmware update that
occur during SBL version check. Current code assume
that the SBL layout does not change between the existing
firmware and the capsule, when the layout change, stage1A
address change and this is causing error while obtaining
the firmware version.
Code is modified to use the last 4 bytes of the SBL region
which contain Stage1A FV address and this is used to obtain
the version information.
Signed-off-by: Raghava <raghava.gudla@intel.com>
during CSME firmware update process, CSME update library throw error
"Could not access PCI device".this patch fixes this issue by adding
back "PciReadBuffer".
TEST=Verified CSME FWU on CFL-H & WHL platforms.
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
This introduces an additional PCI Enumeration option.
- self._PCI_ENUM_FLAG_ALLOC_PMEM_FIRST
By deafult, the option will allocate PCI resource by ascending order
(MEM32->PMEM32->MEM64->PMEM64). If it's set to 1, by reversed order.
Signed-off-by: Aiden Park <aiden.park@intel.com>
The RegionPermission doesn't usually represent the current state of
the Region. There is a need to re-read the permission bit for each
read/write. There by making the variable accurately represents the
HW status.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
In some cases FSP does not support GFX and does not produce
GFX hob. But platform will be able to initialize its GFX after
PCI enumeration. This patch allows splash to be displayed post
PCI if the splash has not been displayed yet.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
jinjhuli