This patch refactors TSN enablement control by
- rename ENABLE_TSN_MAC_ADDRESS with ENABLE_TSN:
align the naming with ENABLE_TCC
- ENABLE_TSN can be used as a one-stop control knob
to reserve FW spaces and include proper TSN CfgData
- collect TSN-specific CfgData into CfgData_Tsn_Feature.dlt
With the new control, inconsistent TSN settings are fixed:
- TSN MAC FW space is reserved but PchTsnEnable is not set
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Some platforms need TempRam Base & Size information to calculate
FspmArchUpd StackBase & Size at runtime.
The TempRam Base & Size info will be only valid until TempRamExit.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Recently, github CI test case, Qemu-linux_boot.py, randomly fails.
Comparing the logs between failed and pass cases, we can find:
1. the failure is caused by timeout before Minimal Linux
completely boots into console and shows "Welcome to Minimal
Linux" messages.
Although such timeout can be a real error (true-positive),
it is also possible just a false alarm (false-positive)...
2. for a failed case, a force push to trigger another CI check
can result in pass, even no code changes. Thus, the timeout
failure points to CI environment (e.g., loading) - a false alarm.
3. the margin (of pass case to timeout) is about 0.4 sec.
This patch increases timeout for 2 seconds to avoid unexpected
test timeout caused CI envornment (e.g., loading).
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Default Bpmgen params created by bpmgen tool
has unicode characters. This patch fixes reading the
file with unicode chars.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
when pin number in pad name is not in <group name><xx> where
xx is pin number format. for example GPIO_VER2_LP_GPP_C2 instead of
GPIO_VER2_LP_GPP_C02, current code has a bug which does not give the
desired output which is GPP_C02.
This patch fixed this issue.
TEST= Verified on multiple platforms that the issue is fixed
Signed-off-by: Raghava <raghava.gudla@intel.com>
This patch clears RTC Alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
This patch also refactors RegRead/RegWrite in RestoreS3RegInfo
to avoid the misalingment of function pointers and coding
convention.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
TSN GBE PMECTRLSTATUS register returned 0x3 after
booting into OS and only occured in Fusa sku
This fix will check TSN PMECTRLSTATUS register and
update value to 0x0 if non-zero value was returned
Only applicable if TSN is enabled
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
CPOC is defined in both Cpu0Hwp.asl and Dsdt/Cpu.asl,
which results in Linux kernel warning and wrong CPU
base speed shown in Windows 10.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
To support rtcm image for all boot options in SBL EHL
Uncomment boot flags and image type in Tcc_Feature.dlt for
enabling tcc in dedicated boot option
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
IA32 build from VS2019 toolchain has security violation
because Digest value from SHA512_384 is not matching the
value calculated and stored in hashstore during build.
Aligning the stack to 32-byte boundary during SHA_Update
fixes this error.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Currently it will return a valid SMMBASE_INFO if SMMBASE_INFO_COMM_ID
is found in SMM S3 resume memory. It will cause issue in S3 path if there
is no one fill correct data when MpInit uses it to rebase SMM.
This patch adds a check to SMMBASE_INFO to avoid this issue.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current index only support up to 0xF as the CFGHDR_TMPL
as it amend into 0x05 (eg. 0x05$(1))
Update the logic to (0x050 + $(1)) instead to support
index larger than 0xF
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
If the capsule file is too small, it should not only
show "the guid is not expected" that may mislead users
using a release-build image. This patch prints out
specific error if opening a small-than-expected capsule.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch replaces the original hard-coded iTBT
root ports enabling control with a CFG option.
The default value is to enable them.
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
Resolve link error when using UsbInitLib
UsbInitLib invokes UsbDeInitBot() which is defined in UsbBlockIoLib
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
Enable DAM option in stitchifwi script for
ITP/CCA debug purpose with -o debug paramter
Example: To enable SATA and DAM enabled "-o sata;debug"
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Update EHL BoardPkg version to 2.0 to allign with current
software package version:
PROJ_MAJOR_VER -> 2 (Maintenance Release candidate)
PROJ_MINOR_VER -> 0 (1st revision of MR1 release)
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Re-enable sbl_rtcm in EHL boot option due to
mistakenly removed it in previous commit of
f01a5b33fb
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This patch provides exampole on how to enable mailbox debug port on
WHL. To enable it, the following needs to be set in BoardConfig.py.
self.DEBUG_OUTPUT_DEVICE_MASK = 0x07
self.CONSOLE_IN_DEVICE_MASK = 0x00000005
self.CONSOLE_OUT_DEVICE_MASK = 0x00000005
Also adjust the PcdMailboxDebugPortMmioBase value in BoardConfig.py
as needed.
On host side, python script can be used in ISD to read/write this
register using IPC interfaces. EX:
import ipccli
ipc = ipccli.baseaccess()
ipc.stateport.cnp_tpsb0.tap2iosfsb32 (...)
Please refere to MailboxDebugPort.py for example.
This was tested on UPX board with CCA debuger connected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows to use a mailbox register (DWORD) to support debug
port. If CCA debug is connected, it is possible to access certain
SOC register through BSSB. Then this register can be used for debug
console input/output.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds DebugPortLib as a platform extention lib to add new
debug port support. It also adds a generic GpioDebugPortLib to allow
GPIO bit bang to emulate UART TX pin.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Enable POSC for all boot medium in Cfgdata_BootOption.yaml
by default
If Non-Fusa sku was detect and the boot flag will
change to exclude POSC
User can modify the boot flag to exclude the POSC in
yaml file as well
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
Add latest Intel® Time Coordinated Computing support for EHL.
Here are the changes:
- Update the TCC subregion layout
- Use the common TCC config data
- Use the common TCC library for RTCT table
- Support TCC DSO cfg, Cache cfg and CRL binaries loading
- Rename TCC variable to follow TCC V2 naming
- Increase the stage 2 size from 0x89000 to 0x91000 to accommodate
the new changes
- Add latest FspmUpd and FspsUpd header files for TCC v2 support
(will be removed once FSP github updated the latest EHL FSP package)
- Change default boot options for RTCM support
TCC mode is turned off by default.
Signed-off-by: Lean Sheng <lean.sheng.tan@intel.com>
Fix mPchSciSupported flag checking before changing the
flag value of boot option.
This bug was introduced from commit
b78cbcf128
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
As per specification of the IAS-Image format
https://github.com/intel/iasimage/blob/master/docs/02_mcd.md
the signature and public key are optional.
As per specification of the header format
https://github.com/intel/iasimage/blob/master/docs/02_mcd.md#image-type
The 8th bit indicate if the signature is included, while the 9th bit
indicates whether the public key is included.
While the previous solution checked if public key is enabled, it did
not check if the signature is included, but rather assumed that it
is always included.
This will lead to a miss-calculation of the `IAS_IMAGE_END` and
`IAS_IMAGE_SIZE` which on the other hand will cause `IsIasImageValid()`
to fail, which will fail the loading of unsigned IAS-Images.
Signed-off-by: Jan Schlosser <jan.schlosser@outlook.com>
Fixed issue #1197
Check PlatformID before proceed to detect from SMBus
Moved PlatformIdInitialize to PostConfigInit
Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
The SBL core revision has not been updated since the creation of
the project. Now with more and more platforms being enabled with
SBL, it is the proper time to upgrade the core revision to be 1.0.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
- Add knob for setting up the ISI configuration file (isi_conf)
- Fix PT test mask value to be aligned with default PT binary
capabilities. Only add mask when PT is enabled.
- "pt" parameter always requires isi_conf file. Dependency added
automatically. isi_conf is also externally configurable since can
be used without PT.
Signed-off-by: Pedro Queiros <pedro.queiros@intel.com>
Add a separate cfgdata dlt file to enable TCC config data.
The TCC dlt file will be appended to board dlt file when
ENABLE_TCC is set in BoardConfig.py.
Removed RTCM subregion and update boot option for RTCM support
TCC is disabled by default.
Signed-off-by: Guo Dong <guo.dong@intel.com>
It will first check the dlt file from source code, it the
dlt file could not be found, then check the build folder.
This enhancement supports the generated dlt file from
build folder.
Signed-off-by: Guo Dong <guo.dong@intel.com>
PreOsChecker is supported in the generic boot flow,
no special code is needed to support PreOsChecker.
So remove these unused code.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
MR2 FSP is available so update SBL to use MR2 FSP.
and also use new Microcode required by new FSP
Update platform code on FSP UPDs, especially enable TCC feature.
Update TGL platform version to 1.2 since MR2 released.
Signed-off-by: Guo Dong <guo.dong@intel.com>
RTCM will sit in OS boot media instead of IFWI image
So update SBL logic to load RTCM from OS boot media.
If the RTCM could not be found, SBL should continue
boot normal OS.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Update EHL BoardPkg version to 1.1 to allign with current
software package version:
PROJ_MAJOR_VER -> 1 (Production Release candidate)
PROJ_MINOR_VER -> 1 (2nd revision of PV release)
Signed-off-by: LeanSheng <lean.sheng.tan@intel.com>
stanley