[EHL] Disable s0ix feature (#1044)
Disable s0ix feature (fsp and fadt flag) until fix is ready. Signed-off-by: Ong Kok Tong <kok.tong.ong@intel.com>
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@ -34,7 +34,7 @@
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Platform/CommonBoardPkg/AcpiTables/Fpdt/Fpdt.aslc
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Ssdt/SaSsdt.asl
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SsdtRtd3/EhlCrbRtd3.asl
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Lpit/Lpit.act
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//Lpit/Lpit.act
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Dmar/Dmar.aslc
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CpuSsdt/Cpu0Cst.asl
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CpuSsdt/Cpu0Hwp.asl
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@ -192,7 +192,7 @@ DefinitionBlock (
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//Include ("PcieDock.asl")
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Include ("PchRpPxsxWrapper.asl")
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Include ("WifiDynamicSar.asl")
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Include ("Pep.asl")
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//Include ("Pep.asl")
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Include ("Psm.asl")
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Include ("Connectivity.asl")
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Include ("MipiCamSensors.asl")
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@ -67,8 +67,7 @@
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EFI_ACPI_6_1_RTC_S4 | \
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EFI_ACPI_6_1_SLP_BUTTON | \
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EFI_ACPI_6_1_PROC_C1 | \
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EFI_ACPI_6_1_RESET_REG_SUP | \
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EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE \
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EFI_ACPI_6_1_RESET_REG_SUP \
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)
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@ -220,9 +220,9 @@ External(WWAN_PCIE_ROOT_PORT.LASX)
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Name(SCLK, 0)
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Store(PS1C, SCLK)
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Include("Rtd3Pcie.asl")
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Scope(\_SB.PC00.RP01.PXSX) {
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Include("Rtd3PcieSsdStorage.asl")
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}
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//Scope(\_SB.PC00.RP01.PXSX) {
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//Include("Rtd3PcieSsdStorage.asl")
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//}
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}
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///
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@ -671,7 +671,7 @@ PlatformUpdateAcpiGnvs (
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PlatformNvs->ApicEnable = 1;
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PlatformNvs->EcAvailable = 0;
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PlatformNvs->LowPowerS0Idle = 1;
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PlatformNvs->LowPowerS0Idle = 0;
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PlatformNvs->TenSecondPowerButtonEnable = 8;
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