Convert the line endings stored for all text files in the repository to
LF. The majority previously used DOS-style CRLF line endings. Add a
.gitattributes file to enforce this and treat certain extensions as
never being text files.
Update PatchCheck.py to insist on LF line endings rather than CRLF.
However, its other checks fail on this commit due to lots of
pre-existing complaints that it only notices because the line endings
have changed.
Silicon/QemuSocPkg/FspBin/Patches/0001-Build-QEMU-FSP-2.0-binaries.patch
needs to be treated as binary since it contains a mixture of line
endings.
This change has implications depending on the client platform you are
using the repository from:
* Windows
The usual configuration for Git on Windows means that text files will
be checked out to the work tree with DOS-style CRLF line endings. If
that's not the case then you can configure Git to do so for the entire
machine with:
git config --global core.autocrlf true
or for just the repository with:
git config core.autocrlf true
Line endings will be normalised to LF when they are committed to the
repository. If you commit a text file with only LF line endings then it
will be converted to CRLF line endings in your work tree.
* Linux, MacOS and other Unices
The usual configuration for Git on such platforms is to check files out
of the repository with LF line endings. This is probably the right thing
for you. In the unlikely even that you are using Git on Unix but editing
or compiling on Windows for some reason then you may need to tweak your
configuration to force the use of CRLF line endings as described above.
* General
For more information see
https://docs.github.com/en/get-started/getting-started-with-git/configuring-git-to-handle-line-endings .
Fixes: https://github.com/slimbootloader/slimbootloader/issues/1400
Signed-off-by: Mike Crowe <mac@mcrowe.com>
This patch implemented SOC specific hook to update the memory
map info through UpdateMemoryInfo() API.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When UART bar is alloaced to 64 bit address, the current SBL API
GetSerialPortBase() only returns the lower 32 bit address, which will
cause problem for UART access. This patch fixed this issue.
Please note the patch did not change the payload HOB interface for
UART info. That needs to be updated to 64bit base address too. But this
patch does not cover that.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Make PchPcrLib common. Remove redundant headers
not used by some platforms and link the new common
lib with the platforms currently using it.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This patch clears RTC alarm when RTC is the S3 wake-up source.
Without clearing it, SMI# will be triggered once SMI_EN is set
by RestoreS3RegInfo, but no handler to clear it which results
in hang.
In addition to clearing RTC SMI#, this patch also clears other
SMI# as UEFI BIOS does.
Test method: rtcwake -m -s 15
Signed-off-by: Stanley Chang <stanley.chang@intel.com>
This patch added PciSegmentLib implementation from EDK2 MdePkg.
This library can be used by silicon libraries to access PCI
device with multiple segments. As part of this change, the
duplicated files were removed for CML and CMLV.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds BdatLib to CommonSocPkg so that all projects
can refer to one single instance of BdatLib. Also removed the
redundant platform-specific package folders.
Signed-off-by: Sai T <sai.kiran.talamudupula@intel.com>
This makes all Platform & Silicon code use APIs to access
LoaderGlobalData instead of accessing variables directly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Inconsistent and redundant header files are removed.
All projects going forward
- Use API declared in GpioLib.h
- Provide instance of GpioSiLib.h
- Use common defines in GpioConfig.h
[QEMU][APL][CFL][CML][CMLV]
- Follow above header model
- Have own instance of GpioLib
[EHL][TGL]
- Follow above header model
- Use common GpioLib instance
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
Use the newly added PchSbiAccessLib in common package,
for all the current platfroms. Platform specific PchSbi Lib
is removed.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
EHL, TGL supports multiple OEM keys and their revocation
by CSE. This patch supports,
- CMDI interface to perform key revocation using
OEMKEYREVOCATION string in cmd file.
- EHL HECI APIs for OemkeyRevoke and to get key status
- FW componets are sorted as per required order.
CSME and BIOS should be signed with new keys and
both components would go together with capsule update.
Signed-off-by: Subash Lakkimsetti <subash.lakkimsetti@intel.com>
This patch fixed a failure in firmware update that
occur during SBL version check. Current code assume
that the SBL layout does not change between the existing
firmware and the capsule, when the layout change, stage1A
address change and this is causing error while obtaining
the firmware version.
Code is modified to use the last 4 bytes of the SBL region
which contain Stage1A FV address and this is used to obtain
the version information.
Signed-off-by: Raghava <raghava.gudla@intel.com>
This patch fixed a failure occured during CSME firmware
update. CSME firmware update library expects PCI read buffer
with a specific format, there is mismatch with input and output
parameter with the current code. Added a wrapper function
with the expected format to fix the failure.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
CFL, CML, EHL, TGL platforms are using PSD version 0.3.
as per PSD Spec v0.3 secureboot status indication as ber below,
000 – Secure boot is Disabled
001 – UEFI Secure boot is enabled
010 – Boot Guard is Enabled
100 – Bootloader Verified boot is Enabled
Signed-off-by: Praveen Hp <praveen.hodagatta.pranesh@intel.com>
During firmware update svn check for SBL region, Current code
assumes that Stage1A base does not change, because of this when
Stage1A base changed in capsule image, getting svn version from
the capsule fails and firmware update is failing.
This patch addressed above issue by reading stage1A base from
capsule image, this way even if stage1A base changes, code will
be able to read it and get svn version from capsule.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Randy Lin