Commit Graph

41 Commits

Author SHA1 Message Date
Victor Sun 25719db8f1 HV: move DRHD data to platform acpi info
In current code, the DRHD data is hardcoded in sbl.c. Replace the data
with MACROs which defined in platform_acpi_info.h as it could be parsed
by offline tool.

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Victor Sun bf834072d4 HV: platform acpi info refactor
Replace platform_acpi_info.c with platform_acpi_info.h and define needed
host ACPI info in MACROs. Then the struct host_acpi_info is not needed
any more.

This header file should be generated by offline tool automatically;

Tracked-On: #1500
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-18 09:26:59 +08:00
Mingqiang Chi 790d8a5ce7 hv:Remove CONFIG_VM0_DESC
If defined CONFIG_VM0_DESC, HV will use predefined vm0_desc
to config VM0,now it is unneccessary, then remove these code.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-10-12 14:41:48 +08:00
Victor Sun b501ce4388 HV: remove dead APIC info MACROs in bsp
These MACROs are never used by current code so remove it. The needed APIC
info is defined in other files with other MACROs.

We will unify kinds of APIC info definition in one place soon.

Tracked-On: #1274

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 15:56:18 +08:00
Victor Sun 2197f4306a HV: Add acpi_fixup api to override acpi on needs
Add acpi_fixup() api in bsp that can override platform ACPI info when
do init_bsp(), this is useful when platform bootloader is not lock
down before production.

In current code only the wake vector addresses would be parsed after
boot and then override to host_acpi_info, we can add more in furture
based on our needs.

Tracked-On: #1264

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 13:34:47 +08:00
Victor Sun a1e9fdc7f9 HV: add Kconfig of CONSTANT_ACPI
If CONFIG_CONSTANT_ACPI is true, then the value in host_acpi_info structure
is constant. Otherwise the host_acpi_info value could be overrided.

This is useful when platform ACPI table value is not fixed in Bootloader
before production.

In production release, this config should be set to yes.

Tracked-On: #1264

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-18 13:34:47 +08:00
Victor Sun dbcbe7d1ff HV: change wake vector to accommodate abl 1820HF1release
MRB bootloader is switched to ABL ver 1820HF1_release, so change platform
acpi info accordingly to support system S3.

Tracked-On: #1196

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-11 16:02:18 +08:00
Victor Sun d8c4619ee9 HV: change wake vector info to accommodate abl
MRB bootloader is switched to ABL, so change platform acpi info accordingly
to support system S3.

Tracked-On: #1196

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-11 08:42:35 +08:00
Victor Sun bb5377b354 HV: change wake vector info to accommodate ww32 sbl
The wake vector address in SBL ACPI table was changed since ww30,
so change platform acpi info accordingly to support system S3.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-15 12:20:28 +08:00
Sainath Grandhi c25a62e5b0 hv: Create E820 entries for OS in partitioning mode ACRN
1) This patch creates static E820 entries for VMs launced by ACRN in
partition mode.
2) Moves vm_description entries from bsp/sbl/ to partition/
3) Removes unused API get_vm_desc_base

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-13 13:58:32 +08:00
Sainath Grandhi 7380c167ed hv: Add vuart flag to VM descriptions in partition mode
ACRN in partition mode emulates UART for the VMs directly launced
from HV. This patch adds an option to enable/disable vUART for a
VM.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-13 09:34:35 +08:00
Sainath Grandhi e40b998d21 hv: Add EPT mapping for UOS in partitioning mode
Adding code to map memory for UOS in partitioning mode ACRN.
HPA starting above 4GB is used for UOS memory. Supports only contiguous memory
from host for UOS. Current implementation supports only 2 GB for UOS memory.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-10 10:22:06 +08:00
Sainath Grandhi ff96453993 hv: Boot multiple OS for Partitioning mode ACRN
ACRN in partitioning mode boots multiple OS. Adding code to parse
VM description structure and a reference description structure for
booting 2 OSes.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-09 15:01:57 +08:00
Jason Chen CJ 589c72382a add CONFIG_VM0_DESC support
if defined CONFIG_VM0_DESC, HV will use predefined vm0_desc to config
VM0, otherwise, HV will run VM0 with all physical cpus.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-25 17:18:14 +08:00
Victor Sun f18a02ac61 HV: misra cleanup for platform acpi info
- fix misra integral type violations;

- change struct initilization style to make code more readable;

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-24 13:45:43 +08:00
Victor Sun ee13110278 HV: change wake vector address to accommodate sbl
- The previous wake vector address just work for ABL, need to change it
  to accommodate the latest SBL;

- Fix wrong bit width value in the pm1a gas;

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-24 13:45:43 +08:00
Junjie Mao 4627cd4de0 HV: build: drop useless files
This patch drops the following useless files in the hypervisor:

* bsp/*/include/: After commit c849bff850 ("HV: config: adapt to the generated
  config.h") these headers are obsolete for configuration. Drop the directories
  and move the generated version.h under $(HV_OBJDIR)/include.

* all_header.c: This is a temporary file for checking violations in headers,
  which is accidentally checked in by commit 3956ce1596 ("HV: io: spell out
  explicit narrowing of integers").

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 14:53:27 +08:00
Huihuang Shi e3302e87e8 HV:transfer vm_hw_logical_core_ids's type and rename it
rename vm_hw_logical_core_ids to vm_pcpu_ids
and changed the type to uint16_t.

V1->V2:rename the vm_hw_logical_core_ids

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-13 13:05:29 +08:00
Jason Chen CJ 6ca99713dd Revert "hv: More changes to enable GPU passthru"
This reverts commit 8d50d40ff8.
2018-07-05 11:06:47 +08:00
Huihuang Shi 2ffa69cb9a HV:misc:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast.

V1->V2:
  a.split patch to patch series

V2->V3:
  a.change the uint64_t type numeric constant's suffix from U to UL

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 12:18:38 +08:00
Anitha Chrisanthus 8d50d40ff8 hv: More changes to enable GPU passthru
Snoop control is not supported in the graphics VT-d engine and so should
be disabled in the PTEs. Also enabled iommu for graphics in the
dmar_drhd array.

v2: removed disable iommu in handle_one_drhd and combined if cond.
v3: minor code review changes
v4: moved the snoop control change to ept.c to accomodate upstream changes
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Gong Zhipeng <zhipeng.gong@intel.com>
2018-06-29 00:50:01 +08:00
Mingqiang Chi 6d46749d0f hv: fix android boot fail on 4GB memory board
Config remained 1GB page to 1 on 4GB memory

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-06-25 12:38:31 +08:00
Junjie Mao aa505a28bb HV: treewide: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-06-21 13:12:39 +08:00
Victor Sun 88e1c4975c HV: add bsp acpi info support
On some occations HV operates relying on host acpi info, we can use a
c file to store this data. The data could be hardcoded or use offline
tool that run on target first and then generate the file automatically.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-13 15:02:03 +08:00
Zide Chen 2a1a6ad0af hv: Other preparation for trampoline code relocation
- For UEFI boot, allocate memory for trampoline code in ACRN EFI,
  and pass the pointer to HV through efi_ctx
- Correct LOW_RAM_SIZE and LOW_RAM_START in Kconfig and bsp_cfg.h
- use trampline_start16_paddr instead of the hardcoded
  CONFIG_LOW_RAM_START for initial guest GDT and page tables

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-06-11 12:15:28 +08:00
Zide Chen 4bb5e60de5 hv: enable MTRR virtualization
- unmask MTRR from guest CPUID to enable MTRR
- MTRR virtualization can be disabled by commenting out CONFIG_MTRR_ENABLED

Signed-off-by: bliu11 <baohong.liu@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-08 12:06:15 +08:00
David B. Kinder f4122d99c5 license: Replace license text with SPDX tag
Replace the BSD-3-Clause boiler plate license text with an SPDX tag.

Fixes: #189

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-06-01 10:43:06 +08:00
Jason Chen CJ 987c7b7511 remove unused parameters in vm_description
vm_attr_name, vm_state_info_privilege & vm_created are not used

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-31 11:27:01 +08:00
Kaige Fu 80a79fed39 HV: Replace printf with pr_acrnlog after logmsg init
There are some massages which is not fatal error but should to print
to serial and sbuf(hvlog) at the same time. pr_fatal is for fatal error
massages and it is not good choice for the situation above.

Introduce a new API pr_acrnlog to deal with the situation. And replace the
following printf with pr_acrnlog for massages should be print to sbuf and
serial. Then developers can get those massages on serial and BTM(Boot Time
Measurement) can use acrnlog to get those massages from sbuf.

BTM refers to Boot Time Measurement which will read acrnlog file to get
timestamps of steps we want.

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:49:09 +08:00
Li, Fei1 6c8fc0a4df hv: remove vm_description_array
When we create an UOS, we didn't indicate the vmid.
Thus we can't get the vm description for the vm
description array.

Instead we use a temporary vm description to save data to
fill the vm structure when crate an UOS. It's uselesss once
UOS has created. So we don't need to maintain vm description
array here for UOS.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
2018-05-30 14:01:56 +08:00
Zide Chen 8f16faab04 HV: further cleanup of header inclusions
According to the comments in hypervisor:
 " This file includes config header file "bsp_cfg.h" and other
	hypervisor used header files.
	It should be included in all the source files."

this patch includes all common header files in hypervisor.h
then removes other redundant inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Zide Chen d594878e31 HV: cleanup for header inclusions.
used https://gitlab.com/esr/deheader to detect and remove unnecessary
header file inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-05-25 10:45:56 +08:00
Jason Chen CJ 8fbb21f7c6 bsp: make hugetlb config enabled by default for SBL platform
switch to hugetlb for SBL platform

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-17 11:33:18 +08:00
lijinxia 3b6fe5782d Revert "HV: Prepare cpu_secondary.S for AP trampoline code relocation"
This reverts commit bfa67fa6a0.
2018-05-15 17:25:59 +08:00
lijinxia b3dd135ed3 Revert "HV: added memory allocation functions for AP trampoline code relocation"
This reverts commit 41b83bb20b.
2018-05-15 17:25:58 +08:00
Zide Chen ceb3076b69 HV: added memory allocation functions for AP trampoline code relocation
V2->V3: Fixed the booting issue on MRB board and removed the restriction
        of allocate memory from address 0

1) Fix the booting from MRB issue
-#define    CONFIG_LOW_RAM_SIZE 0x000CF000
+#define    CONFIG_LOW_RAM_SIZE 0x00010000

2) changed e820_alloc_low_memory() to handle corner case of unaligned e820 entries
  and enable it to allocate memory at address 0
+		a length = end > start ? (end - start) : 0;

-       /* We don't want the first page */
-       if ((length == size) && (start == 0))
-           continue;

3) changed emalloc_for_low_mem() to enable to allocate memory at address 0
-       /* We don't want the first page */
-       if (start == 0)
-           start = EFI_PAGE_SIZE;

V1->V2: moved e820_alloc_low_memory() to guest.c and added the logic to
        handle unaligned E820 entries

emalloc_for_low_mem() is used if CONFIG_EFI_STUB is defined.
e820_alloc_low_memory() is used for other cases

In either case, the allocated memory will be marked with E820_TYPE_RESERVED

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Zide Chen 9323f811ea HV: Prepare cpu_secondary.S for AP trampoline code relocation
V1->V2: removed CONFIG_LOW_RAM_START and added ".org 0" to
cpu_secondary.S

The assumption is trampoline code is relocated while HV is not, so:

trampoline code is built at address 0, and CS register is updated
by SIPI to reflect the correct vector

in real mode part, added extra pointers for page tables and long jump buffer
so it's possible for HV code to patch the relocation offset

in long mode part, use absolute addressing when referring HV symbols,
and use relative addressing for symbols within trampoline code

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:58 +08:00
Minggui Cao f8a26a69e9 remove deadcode of vm1 config in vm_description
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:56 +08:00
Jason Chen CJ a1c6c24248 vm load: add SOS cmdline option for hugetlb
adding "hugepagesz=1G" and "hugepages=X" into SOS cmdline, for X, current
strategy is making it equal
	e820_mem.total_mem_size -CONFIG_REMAIN_1G_PAGES
if CONFIG_REMAIN_1G_PAGES is not set, it will use 3 by default.

CONFIG_CMA is added to indicate using cma cmdline option for SOS kernel,
by default system will use hugetlb cmdline option if no CONFIG_CMA defined.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
2018-05-15 17:25:56 +08:00
Jason Chen CJ d14a7dbdd2 retpoline: add indirect thunk support
for gcc version > 7.3, enable CONFIG_RETPOLINE

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:36 +08:00
Eddie Dong 7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00