61 lines
1.1 KiB
ArmAsm
61 lines
1.1 KiB
ArmAsm
/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/riscv/csr.h>
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#include <nuclei/nuclei_csr.h>
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GTEXT(__nuclei_start)
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SECTION_FUNC(vectors, __nuclei_start)
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/* Disable Global Interrupt */
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csrc mstatus, MSTATUS_MIE
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/* Jump to logical address first to ensure correct operation of RAM region */
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la a0, __nuclei_start
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li a1, 1
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slli a1, a1, 29
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bleu a1, a0, _start0800
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srli a1, a1, 2
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bleu a1, a0, _start0800
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la a0, _start0800
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add a0, a0, a1
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jr a0
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_start0800:
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#if defined(CONFIG_RISCV_GP)
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/* Initialize global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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#endif
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.option norvc;
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/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
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li t0, 0x200
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csrs CSR_MMISC_CTL, t0
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/* Initial the CSR MTVEC for the Trap ane NMI base addr */
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la t0, trap_entry
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csrw mtvec, t0
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/* Direct Mode: All exceptions set pc to BASE. */
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csrc mtvec, 0x3
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/* Disable performance counter */
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csrsi mcountinhibit, 0x5
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/* Jump to __reset */
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tail __reset
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1:
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j 1b
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.align 6
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trap_entry:
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tail _isr_wrapper
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