Gerard Marull-Paretas 014d831d80 soc: arm/riscv: gigadevice: enable reset controller by default ... Similar to pinctrl, almost all device drivers will depend on the reset controller being available, so default the driver class to y at SoC level. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2022-08-29 10:30:49 +02:00
..
andes_v5	soc: riscv: andes_v5: use syscon driver instead of accessing dts directly	2022-08-23 10:15:50 +02:00
common	soc: riscv: remove usage of SOC_ERET	2022-08-04 13:44:48 +02:00
gd32vf103	soc: arm/riscv: gigadevice: enable reset controller by default	2022-08-29 10:30:49 +02:00
miv	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
mpfs	soc: riscv: mpfs: remove unused definition	2022-08-02 09:12:31 +02:00
neorv32	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
sifive-freedom	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
starfive_jh71xx	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
telink_b91	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
virt	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00
CMakeLists.txt	…
Kconfig	Kconfig: Introduce RISCV_HAS_CLIC	2022-07-11 14:31:39 +02:00
Kconfig.defconfig	…
Kconfig.soc	…