Gerard Marull-Paretas 014d831d80 soc: arm/riscv: gigadevice: enable reset controller by default ... Similar to pinctrl, almost all device drivers will depend on the reset controller being available, so default the driver class to y at SoC level. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2022-08-29 10:30:49 +02:00
..
CMakeLists.txt	…
Kconfig.defconfig.gd32vf103	soc: arm/riscv: gigadevice: enable reset controller by default	2022-08-29 10:30:49 +02:00
Kconfig.defconfig.series	…
Kconfig.series	Kconfig: Introduce RISCV_HAS_CLIC	2022-07-11 14:31:39 +02:00
Kconfig.soc	riscv: Rework and cleanup Kconfig	2022-06-05 14:28:42 +02:00
entry.S	riscv: Rename __irq_wrapper to _isr_wrapper	2022-06-21 20:27:20 -04:00
linker.ld	linker: update files with <zephyr/...> include prefix	2022-05-09 12:45:29 -04:00
pinctrl_soc.h	…
soc.c	soc: riscv: gd32vf103: add missing include	2022-07-28 20:50:57 +02:00
soc.h	soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions	2022-08-02 09:12:31 +02:00