157 lines
3.5 KiB
ArmAsm
157 lines
3.5 KiB
ArmAsm
/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "asm_ldo_management.h"
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#include "asm_memory_management.h"
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#include "adsp_memory.h"
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#define IPC_HOST_BASE 0x00071E00
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#define IPC_DIPCIDD 0x18
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#define IPC_DIPCIDR 0x10
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.section .text, "ax"
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.align 64
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power_down_literals:
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.literal_position
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set_dx_reply:
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/* BUSY (bit31), MODULE_MSG (bit30), reply (bit29), SET_DX (bit 24-28: 7) */
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.word 0xE7000000
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sram_dis_loop_cnt:
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.word 4096
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.global power_down_cavs
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.type power_down_cavs, @function
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/**
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* Perform power down.
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*
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* Depending on arguments, memories are switched off.
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* A2 - argument for LPSRAM
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* A3 - pointer to array containing power gating mask.
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*Size of array is determined by MEMORY_SEGMENTS define.
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* A4 - platform type
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* A5 - response_to_ipc
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*/
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#define b_enable_lpsram a2
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#define pu32_hpsram_mask a3
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#define temp_reg0 a6
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#define temp_reg1 a7
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#define temp_reg2 a8
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#define temp_reg3 a9
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#define host_base a10
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#define pfl_reg a15
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power_down_cavs:
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entry sp, 32
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/**
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* effectively executes:
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* xthal_dcache_region_lock(&literals, 128);
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* xthal_icache_region_lock(&powerdown, 256);
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* xthal_dcache_region_lock(&pu32_hpsram_mask, 64);
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*/
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movi pfl_reg, power_down_literals
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dpfl pfl_reg, 0
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dpfl pfl_reg, 64
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movi pfl_reg, power_down_cavs
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ipfl pfl_reg, 0
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ipfl pfl_reg, 64
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ipfl pfl_reg, 128
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ipfl pfl_reg, 192
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mov pfl_reg, pu32_hpsram_mask
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dpfl pfl_reg, 0
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movi host_base, IPC_HOST_BASE
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_PD_DISABLE_LPSRAM:
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/* effectively executes:
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* if (b_enable_lpsram){
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* cavs_lpsram_power_down_entire();
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* }
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*/
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beqz b_enable_lpsram, _PD_DISABLE_HPSRAM
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m_cavs_lpsram_power_down_entire temp_reg0, temp_reg1, temp_reg2, sram_dis_loop_cnt
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j _PD_DISABLE_HPSRAM
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_PD_DISABLE_HPSRAM:
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/* if value in memory pointed by pu32_hpsram_mask = 0
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(hpsram_pwrgating_mask) - do not disable hpsram. */
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beqz pu32_hpsram_mask, _PD_SEND_IPC
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/* mandatory sequence for LDO ON - effectively executes:
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* m_cavs_s_set_ldo_hpsram_on_state();
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* WAIT_300NS();
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*/
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movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_ON
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m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
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movi temp_reg0, 128
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1 :
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addi temp_reg0, temp_reg0, -1
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bnez temp_reg0, 1b
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/* effectively executes:
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* for (size_t seg_index = (MAX_MEMORY_SEGMENTS - 1); seg_index >= 0;
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* --seg_index) {
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* cavs_hpsram_power_change(seg_index, mask[seg_index]);
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* }
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* where mask is given in pu32_hpsram_mask register
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*/
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.set seg_index, HPSRAM_SEGMENTS - 1
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.rept HPSRAM_SEGMENTS
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l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index
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m_cavs_hpsram_power_change\
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/*segment_index=*/ seg_index,\
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/*mask=*/ temp_reg0,\
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temp_reg1,\
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temp_reg2,\
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temp_reg3
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.set seg_index, seg_index - 1
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.endr
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/* mandatory sequence for LDO OFF - effectively executes:
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* WAIT_300NS();
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* m_cavs_set_ldo_hpsram_on_state()
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*/
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movi temp_reg0, 128
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1 :
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addi temp_reg0, temp_reg0, -1
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bnez temp_reg0, 1b
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movi temp_reg0, SHIM_LDOCTL_HPSRAM_LDO_OFF
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m_cavs_set_hpldo_state temp_reg0, temp_reg1, temp_reg2
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_PD_SEND_IPC:
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/* Send IPC reply for SET_DX message */
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movi temp_reg1, 0
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s32i temp_reg1, host_base, IPC_DIPCIDD
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movi temp_reg1, set_dx_reply
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l32i temp_reg1, temp_reg1, 0
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s32i temp_reg1, host_base, IPC_DIPCIDR
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_PD_SLEEP:
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/* effecfively executes:
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* xmp_spin()
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* waiti 5
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*/
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movi temp_reg0, 128
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loop:
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addi temp_reg0, temp_reg0, -1
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bnez temp_reg0, loop
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extw
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extw
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waiti 5
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1:
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j 1b
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.size power_down_cavs , . - power_down_cavs
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