392 lines
9.5 KiB
Plaintext
392 lines
9.5 KiB
Plaintext
/*
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* Copyright (c) 2023 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu4: cpu@4 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <4>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu5: cpu@5 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <5>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu5_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu6: cpu@6 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <6>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu6_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu7: cpu@7 {
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compatible = "andestech,andescore-v5", "riscv";
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device_type = "cpu";
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reg = <7>;
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status = "okay";
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riscv,isa = "rv32gc_xandes";
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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cpu7_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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dram: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00000000 0x40000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "andestech,ae350";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe4000000 0x02000000>;
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11
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&cpu2_intc 11 &cpu3_intc 11
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&cpu4_intc 11 &cpu5_intc 11
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&cpu6_intc 11 &cpu7_intc 11>;
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};
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plic_sw: interrupt-controller@e6400000 {
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compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6400000 0x00400000>;
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riscv,max-priority = <255>;
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riscv,ndev = <1023>;
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interrupts-extended = <&cpu0_intc 3 &cpu1_intc 3
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&cpu2_intc 3 &cpu3_intc 3
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&cpu4_intc 3 &cpu5_intc 3
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&cpu6_intc 3 &cpu7_intc 3>;
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#size-cells = <0>;
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mbox: mbox-controller@0 {
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compatible = "andestech,mbox-plic-sw";
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#mbox-cells = <1>;
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reg = <0>;
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interrupts = <9 1>, <10 1>, <11 1>, <12 1>,
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<13 1>, <14 1>, <15 1>, <16 1>,
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<17 1>, <18 1>, <19 1>, <20 1>,
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<21 1>, <22 1>, <23 1>, <24 1>,
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<25 1>, <26 1>, <27 1>, <28 1>,
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<29 1>, <30 1>, <31 1>;
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interrupt-names = "mbox_9", "mbox_10", "mbox_11", "mbox_12",
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"mbox_13", "mbox_14", "mbox_15", "mbox_16",
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"mbox_17", "mbox_18", "mbox_19", "mbox_20",
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"mbox_21", "mbox_22", "mbox_23", "mbox_24",
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"mbox_25", "mbox_26", "mbox_27", "mbox_28",
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"mbox_29", "mbox_30", "mbox_31";
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interrupt-parent = <&plic_sw>;
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status = "disabled";
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};
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};
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mtimer: timer@e6000000 {
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compatible = "andestech,machine-timer";
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reg = <0xe6000000 0x10>;
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interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
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&cpu2_intc 7 &cpu3_intc 7
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&cpu4_intc 7 &cpu5_intc 7
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&cpu6_intc 7 &cpu7_intc 7>;
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};
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syscon: syscon@f0100000 {
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compatible = "syscon", "andestech,atcsmu100";
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reg = <0xf0100000 0x1000>;
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status = "disabled";
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};
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l2_cache: cache-controller@e0500000 {
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compatible = "andestech,l2c";
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reg = <0xe0500000 0x1000>;
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status = "disabled";
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};
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uart0: serial@f0200020 {
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compatible = "ns16550";
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reg = <0xf0200020 0x1000>;
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reg-shift = <2>;
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interrupts = <8 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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uart1: serial@f0300020 {
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compatible = "ns16550";
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reg = <0xf0300020 0x1000>;
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reg-shift = <2>;
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interrupts = <9 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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pit0: pit@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0xf0400000 0x1000>;
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interrupts = <3 1>;
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interrupt-parent = <&plic0>;
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clock-frequency = <60000000>;
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prescaler = <600>;
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status = "disabled";
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};
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rtc0: rtc@f0600000 {
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compatible = "andestech,atcrtc100";
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reg = <0xf0600000 0x1000>;
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interrupts = <1 1>, <2 1>;
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interrupt-parent = <&plic0>;
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wakeup-source;
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status = "disabled";
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};
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gpio0: gpio@f0700000 {
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compatible = "andestech,atcgpio100";
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reg = <0xf0700000 0x1000>;
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interrupts = <7 1>;
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interrupt-parent = <&plic0>;
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gpio-controller;
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ngpios = <32>;
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#gpio-cells = <2>;
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status = "disabled";
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};
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i2c0: i2c@f0a00000 {
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compatible = "andestech,atciic100";
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reg = <0xf0a00000 0x1000>;
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interrupts = <6 1>;
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interrupt-parent = <&plic0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0xf0b00000 0x1000
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0x80000000 DT_SIZE_K(1024)>;
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reg-names = "control", "mem";
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interrupts = <4 1>;
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interrupt-parent = <&plic0>;
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dmas = <&dma0 0 0 0x009>,
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<&dma0 1 1 0x00A>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <66000000>;
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status = "disabled";
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};
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spi1: spi@f0f00000 {
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compatible = "andestech,atcspi200";
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reg = <0xf0f00000 0x1000>;
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reg-names = "control";
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interrupts = <5 1>;
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interrupt-parent = <&plic0>;
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dmas = <&dma0 2 2 0x009>,
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<&dma0 3 3 0x00A>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <66000000>;
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status = "disabled";
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmac300";
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reg = <0xf0c00000 0x1000>;
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interrupts = <10 1>;
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interrupt-parent = <&plic0>;
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dma-channels = <8>;
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dma-requests = <16>;
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chain-transfer = <1>;
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#dma-cells = <3>;
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status = "disabled";
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};
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eth0: eth@e0100000 {
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compatible = "andestech,atfmac100";
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reg = <0xe0100000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&plic0>;
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local-mac-address = [FC 8C EB 9B A6 51];
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status = "disabled";
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};
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lcd0: lcd@e0200000 {
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compatible = "andestech,atflcdc100";
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reg = <0xe0200000 0x1000>;
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interrupts = <20 1>;
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interrupt-parent = <&plic0>;
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clock-frequency = <30000000>;
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status = "disabled";
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};
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wdt: wdt@f0500000 {
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compatible = "andestech,atcwdt200";
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reg = <0xf0500000 0x1000>;
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interrupts = <20 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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smc0: smc@e0400000 {
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compatible = "andestech,atfsmc020";
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reg = <0xe0400000 0x1000>;
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status = "disabled";
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};
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snd0: snd@f0d00000 {
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compatible = "andestech,atfac97";
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reg = <0xf0d00000 0x1000>;
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interrupts = <17 1>;
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interrupt-parent = <&plic0>;
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status = "disabled";
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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reg = <0xf0e00000 0x1000>;
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interrupts = <18 1>;
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interrupt-parent = <&plic0>;
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cap-sd-highspeed;
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max-frequency = <100000000>;
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clock-freq-min-max = <400000 100000000>;
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fifo-depth = <0x10>;
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status = "disabled";
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};
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};
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};
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