ecf308e8de
This commit adjusts the sizes of the two PLIC nodes AE350 defines: * `plic0` size is changed from `0x04000000` to `0x02000000` * `plic_sw` size is changed from `0x04000000` to `0x00400000` Without these change, `plic0` address space would overlap with `plic_sw`, and with other memory-mapped peripherals. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> |
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| andes | ||
| efinix | ||
| espressif | ||
| gd | ||
| ite | ||
| lowrisc | ||
| microchip | ||
| niosv | ||
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| openisa | ||
| qemu | ||
| sensry | ||
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| neorv32.dtsi | ||
| renode_riscv32_virt.dtsi | ||
| riscv32-litex-vexriscv.dtsi | ||