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dts/andes: adjust the sizes of PLIC nodes 

This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`

Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-10-29 12:22:04 +01:00 committed by Mahesh Mahadevan
parent 63890e2526
commit ecf308e8de
1 changed files with 2 additions and 2 deletions
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4
dts/riscv/andes/andes_v5_ae350.dtsi
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@ -170,7 +170,7 @@
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe4000000 0x04000000>;
reg = <0xe4000000 0x02000000>;
riscv,max-priority = <255>;
riscv,ndev = <1023>;
interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11
@ -184,7 +184,7 @@
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe6400000 0x04000000>;
reg = <0xe6400000 0x00400000>;
riscv,max-priority = <255>;
riscv,ndev = <1023>;
interrupts-extended = <&cpu0_intc 3 &cpu1_intc 3